Neuromorphic Hardware Systems Research Articles

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

2D Materials-based Neuromorphic Computing Electronic Device

Nowadays, with the rapid information explosion connected to all devices, there is a huge demand for effectively processing big data. In particular, conventional von Neumann computing system with physically separated processing and memory units face significant problems in dealing with massive unstructured data such as sound, images, and video because of a von Neumann bottleneck. As a key feature of parallel operations, neuromorphic computing systems can analyze massive unstructured data in a time and energy efficient manner. However, critical issues related to reliability and variability of nonlinearity and asymmetric weight update, have been great challenges in the implementation of artificial synaptic device in practical neuromorphic hardware system. Also, hardware systems enabling artificial neural networks in-situ personal data are essential for adaptive wearable neuromorphic edge computing.

An ultrasmall organic synapse for neuromorphic computing

High‐performance organic neuromorphic devices with miniaturized device size and computing capability are essential elements for developing brain‐inspired humanoid intelligence technique. However, due to the structural inhomogeneity of most organic materials, downscaling of such devices to nanoscale and their high‐density integration into compact matrices with reliable device performance remain challenging at the moment. Herein, based on the design of a semicrystalline polymer PBFCL10 with ordered structure to regulate dense and uniform formation of conductive nanofilaments, we realize an organic synapse with the smallest device dimension of 50 nm and highest integration size of 1 Kb reported thus far. The as‐fabricated PBFCL10 synapses can switch between 32 conductance states linearly with a high cycle‐to‐cycle uniformity of 98.89% and device‐to‐device uniformity of 99.71%, which are the best results of organic devices. A mixed-signal neuromorphic hardware system based on the organic neuromatrix and FPGA controller is implemented to execute spiking‐plasticity‐related algorithm for decision-making tasks.

Nonvolatile and volatile resistive switching characteristics in MoS2 thin film for RRAM application

Resistive random access memory (RRAM) is one of strong candidates for future memory technology. The volatile and nonvolatile properties of devices are important foundations for the construction of neuromorphic hardware systems, which still represents a challenge. In this study, we fabricated the Cu/MoS2/ITO RRAM by RF magnetic sputtering with different thicknesses of MoS2 thin films, and explored the possibility of obtaining the nonvolatile and volatile memristive effects of RRAM devices through different operating voltages. By systematically investigating the resistive switching (RS) characteristics, we proposed and discussed the nonvolatile and volatile conceptual models to elaborate on the RS mechanism of the fabricated devices. The nonvolatile and volatile behaviors were explained respectively by the forming and breaking of Cu conductive filaments between Cu and ITO, and the trapping and de-trapping of electrons leading to the change of the Schottky barrier at the ITO/MoS2 interface.

Astromorphic Self-Repair of Neuromorphic Hardware Systems

While neuromorphic computing architectures based on Spiking Neural Networks (SNNs) are increasingly gaining interest as a pathway toward bio-plausible machine learning, attention is still focused on computational units like the neuron and synapse. Shifting from this neuro-synaptic perspective, this paper attempts to explore the self-repair role of glial cells, in particular, astrocytes. The work investigates stronger correlations with astrocyte computational neuroscience models to develop macro-models with a higher degree of bio-fidelity that accurately captures the dynamic behavior of the self-repair process. Hardware-software co-design analysis reveals that bio-morphic astrocytic regulation has the potential to self-repair hardware realistic faults in neuromorphic hardware systems with significantly better accuracy and repair convergence for unsupervised learning tasks on the MNIST and F-MNIST datasets. Our implementation source code and trained models are available at https://github.com/NeuroCompLab-psu/Astromorphic_Self_Repair.

Wi-Fi frame detection via spiking neural networks with memristive synapses

With increasing performance of deep learning, researchers have employed Deep Neural Networks (DNNs) for wireless communications. In particular, mechanisms for detecting Wi-Fi frames that use DNNs demonstrate their excellent performances in terms of detection accuracy. However, DNNs require significant amount of computation resources. Thus, if the DNN-based mechanisms are used in mobile devices or low-end devices, their battery would be quickly depleted. Spiking Neural Networks (SNNs), which are regarded as the next generation of neural network, have advantages over DNNs: low energy consumption and limited computational complexity. Motivated by these advantages, in this paper, we propose a mechanism to detect a Wi-Fi frame using SNNs and show the feasibility of SNNs for Wi-Fi detection. The mechanism is composed of a preprocessing module for converting collected signals and an SNN module for detecting Wi-Fi frames. The SNN module employs Leaky Integrate-and-Fire (LIF) neurons and Spike-Timing-Dependent Plasticity (STDP) learning rule. To reflect the features of an actual neuromorphic hardware system, our SNN module considers memristive synaptic features such as non-linear weight updates. Our experimental study demonstrates the detection capabilities of the proposed mechanism are comparable to those of previous mechanisms that use DNNs, CNNs and RNNs while consuming definitely less energy than the previous mechanism.

Spiking Neural Network Nonlinear Demapping on Neuromorphic Hardware for IM/DD Optical Communication

Neuromorphic computing implementing spiking neural networks (SNN) is a promising technology for reducing the footprint of optical transceivers, as required by the fast-paced growth of data center traffic. In this work, an SNN nonlinear demapper is designed and evaluated on a simulated intensity-modulation direct-detection link with chromatic dispersion. The SNN demapper is implemented in software and on the analog neuromorphic hardware system BrainScaleS-2 (BSS-2). For comparison, linear equalization (LE), Volterra nonlinear equalization (VNLE), and nonlinear demapping by an artificial neural network (ANN) implemented in software are considered. At a pre-forward error correction bit error rate of exponent-product2e-3, the software SNN outperforms LE by 1.5 dB, VNLE by 0.3 dB and the ANN by 0.5 dB. The hardware penalty of the SNN on BSS-2 is only 0.2 dB, i.e., also on hardware, the SNN performs better than all software implementations of the reference approaches. Hence, this work demonstrates that SNN demappers implemented on electrical analog hardware can realize powerful and accurate signal processing fulfilling the strict requirements of optical communications.

Memory-Dependent Computation and Learning in Spiking Neural Networks Through Hebbian Plasticity.

Spiking neural networks (SNNs) are the basis for many energy-efficient neuromorphic hardware systems. While there has been substantial progress in SNN research, artificial SNNs still lack many capabilities of their biological counterparts. In biological neural systems, memory is a key component that enables the retention of information over a huge range of temporal scales, ranging from hundreds of milliseconds up to years. While Hebbian plasticity is believed to play a pivotal role in biological memory, it has so far been analyzed mostly in the context of pattern completion and unsupervised learning in artificial and SNNs. Here, we propose that Hebbian plasticity is fundamental for computations in biological and artificial spiking neural systems. We introduce a novel memory-augmented SNN architecture that is enriched by Hebbian synaptic plasticity. We show that Hebbian enrichment renders SNNs surprisingly versatile in terms of their computational as well as learning capabilities. It improves their abilities for out-of-distribution generalization, one-shot learning, cross-modal generative association, language processing, and reward-based learning. This suggests that powerful cognitive neuromorphic systems can be built based on this principle.

Robust 2D MoS2 Artificial Synapse Device Based on a Lithium Silicate Solid Electrolyte for High-Precision Analogue Neuromorphic Computing.

High-precision artificial synaptic devices compatible with existing CMOS technology are essential for realizing robust neuromorphic hardware systems with reliable parallel analogue computation beyond the von Neumann serial digital computing architecture. However, critical issues related to reliability and variability, such as nonlinearity and asymmetric weight updates, have been great challenges in the implementation of artificial synaptic devices in practical neuromorphic hardware systems. Herein, a robust three-terminal two-dimensional (2D) MoS2 artificial synaptic device combined with a lithium silicate (LSO) solid-state electrolyte thin film is proposed. The rationally designed synaptic device exhibits excellent linearity and symmetry upon electrical potentiation and depression, benefiting from the reversible intercalation of Li ions into the MoS2 channel. In particular, extremely low cycle-to-cycle variations (3.01%) during long-term potentiation and depression processes over 500 pulses are achieved, causing statistical analogue discrete states. Thus, a high classification accuracy of 96.77% (close to the software baseline of 98%) is demonstrated in the Modified National Institute of Standards and Technology (MNIST) simulations. These results provide a future perspective for robust synaptic device architecture of lithium solid-state electrolytes stacked with 2D van der Waals layered channels for high-precision analogue neuromorphic computing systems.

Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning

Local learning schemes have shown promising performance in spiking neural networks (SNNs) training and are considered a step toward more biologically plausible learning. Despite many efforts to design high-performance neuromorphic systems, a fast and efficient on-chip training algorithm is still missing, which limits the deployment of neuromorphic systems in many real-time applications. This work proposes a scalable, fast, and efficient spiking neuromorphic hardware system with on-chip local learning capability. We introduce an effective hardware-friendly local training algorithm compatible with sparse temporal input coding and binary random classification weights. The algorithm is demonstrated to deliver competitive accuracy in different tasks. The proposed digital system explores spike sparsity in communication, parallelism in vector–matrix operations and process-level dataflow, and locality of training errors, which leads to low cost and fast training speed. The system is optimized under various performance metrics. Taking into consideration energy, speed, resources, and accuracy, the proposed method shows around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> efficiency over a recent work with a direct feedback alignment (DFA) method and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> efficiency over the spike-timing-dependent plasticity (STDP) method. Moreover, our hardware architecture can easily scale up with the network size at a linear rate. Thus, our method has demonstrated great potential for use in various applications, especially those demanding low latency.

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

AbstractNonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device.

Connectivity concepts in neuronal network modeling.

Sustainable research on computational models of neuronal networks requires published models to be understandable, reproducible, and extendable. Missing details or ambiguities about mathematical concepts and assumptions, algorithmic implementations, or parameterizations hinder progress. Such flaws are unfortunately frequent and one reason is a lack of readily applicable standards and tools for model description. Our work aims to advance complete and concise descriptions of network connectivity but also to guide the implementation of connection routines in simulation software and neuromorphic hardware systems. We first review models made available by the computational neuroscience community in the repositories ModelDB and Open Source Brain, and investigate the corresponding connectivity structures and their descriptions in both manuscript and code. The review comprises the connectivity of networks with diverse levels of neuroanatomical detail and exposes how connectivity is abstracted in existing description languages and simulator interfaces. We find that a substantial proportion of the published descriptions of connectivity is ambiguous. Based on this review, we derive a set of connectivity concepts for deterministically and probabilistically connected networks and also address networks embedded in metric space. Beside these mathematical and textual guidelines, we propose a unified graphical notation for network diagrams to facilitate an intuitive understanding of network properties. Examples of representative network models demonstrate the practical use of the ideas. We hope that the proposed standardizations will contribute to unambiguous descriptions and reproducible implementations of neuronal network connectivity in computational neuroscience.

A Learning-Rate Modulable and Reliable TiOx Memristor Array for Robust, Fast, and Accurate Neuromorphic Computing.

Realization of memristor‐based neuromorphic hardware system is important to achieve energy efficient bigdata processing and artificial intelligence in integrated device system‐level. In this sense, uniform and reliable titanium oxide (TiO x ) memristor array devices are fabricated to be utilized as constituent device element in hardware neural network, representing passive matrix array structure enabling vector‐matrix multiplication process between multisignal and trained synaptic weight. In particular, in situ convolutional neural network hardware system is designed and implemented using a multiple 25 × 25 TiO x memristor arrays and the memristor device parameters are developed to bring global constant voltage programming scheme for entire cells in crossbar array without any voltage tuning peripheral circuit such as transistor. Moreover, the learning rate modulation during in situ hardware training process is successfully achieved due to superior TiO x memristor performance such as threshold uniformity (≈2.7%), device yield (> 99%), repetitive stability (≈3000 spikes), low asymmetry value of ≈1.43, ambient stability (6 months), and nonlinear pulse response. The learning rate modulable fast‐converging in situ training based on direct memristor operation shows five times less training iterations and reduces training energy compared to the conventional hardware in situ training at ≈95.2% of classification accuracy.

Defect generation in a data-storage layer by strong ion bombardment for multilevel non-volatile memory applications

Neuromorphic devices and systems have been widely studied for future computing platforms. For an accurate neural network, each memory cell in the system requires multilevel data to support sufficient weight levels. However, conventional memory devices have limitations in increasing the data levels while maintaining low power consumption. In this study, we demonstrate that a strong ion bombardment process can be a viable solution for multilevel memory. During sputter deposition of a data-storage layer in charge trap flash, a substrate bias increases the total trap density by 64%, which significantly enhances the memory window and data levels. From secondary ion mass spectrometry and X-ray photoelectron spectroscopy, we reveal that the origin of the increase in trap states is the ejection of O atoms by the bombardment process. The present work provides a novel strategy to increase the data levels of a memory device, and thus, paves the way for reliable neuromorphic hardware system.

A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning

For embedded, mobile and edge-computing intelligent applications, this brief proposes a low-cost real-time neuromorphic hardware system of spiking Extreme Learning Machine (ELM) equipped with on-chip triplet-based reward-modulated spike-timing-dependent plasticity (R-STDP) learning capability. Our design employs a time-step pipelined dual-core architecture consisting of parallel computing unit arrays to improve processing speed, as well as a trace-assisting learning mechanism and on-the-fly hidden layer weight re-generators to significantly reduce hardware resource costs. Our architecture is scalable to different spiking ELM sizes under different tradeoffs among processing speed, recognition accuracy and resource costs. Tests showed that the on-chip triplet R-STDP learning capability can help to achieve relatively high recognition accuracies on our hardware system. An FPGA prototype with low logic and memory resource consumption was implemented, achieving 93% and 78.5% recognition accuracies on the MNIST and Fashion-MNIST image datasets, respectively, at a speed of 30 frames per second (fps) for inference and 22.5 fps for on-chip learning.

Prospect and challenges of analog switching for neuromorphic hardware

To inaugurate energy-efficient hardware as a solution to complex tasks, information processing paradigms shift from von Neumann to non-von Neumann computing architectures. Emerging electronic devices compete with speed, energy, and performance to revolutionize the neural hardware system where training and inference must achieve milestones. In this Perspective, we discuss the essential criteria for training and inference in various nonvolatile neuromorphic systems such as filamentary resistive switching, interfacial resistive switching, electrochemical random-access memory, and ferroelectric memory. We present a holistic analysis of technical requirements to design ideal neuromorphic hardware in which linearity is the critical aspect during training, whereas retention is the essential criterion of inference. Finally, we evaluate the prospect of a futuristic neuromorphic hardware system by optimizing the training and inference dilemma.

Ultralow‐Power Synaptic Transistors Based on Ta2O5/Al2O3 Bilayer Dielectric for Algebraic Arithmetic

AbstractMultifarious artificial synaptic devices are extensively proposed in the field of neuromorphic hardware systems for their applicability in promising parallel computer architecture, which is preferred to classical Von Neumann architecture in numerous and complex information processing. Besides the ability to mimic typical biological synaptic behaviors, low power consumption is critical for the synaptic devices in the neuromorphic hardware system.In this paper, ultralow‐power Ta2O5/Al2O3 bilayer‐gate‐dielectric synaptic transistors (TABSTs) with low‐temperature atomic layer deposited dielectric are proposed. The TABSTs show power consumption as low as 19.9 aJ per synaptic event successfully at a low drain voltage of 0.001 V and a short pulse width of 1 ms. Essential synaptic behaviors including excitatory postsynaptic current, inhibitory postsynaptic current, spike‐amplitude‐dependent plasticity, spike‐duration‐dependent plasticity, paired pulse facilitation, long‐term potentiation, long‐term depression, the transition from short‐term memory to long‐term memory as well as learning and forgetting abilities are well mimicked by the TABSTs. Moreover, algebraic arithmetic operations such as addition, subtraction, multiplication, and division are also implemented by the TABSTs. This work provides a promising approach to emerging neuromorphic systems.

Tailoring the synaptic properties of a-IGZO memristors for artificial deep neural networks

Neuromorphic computation based on resistive switching devices represents a relevant hardware alternative for artificial deep neural networks. For the highest accuracies on pattern recognition tasks, an analog, linear, and symmetric synaptic weight is essential. Moreover, the resistive switching devices should be integrated with the supporting electronics, such as thin-film transistors (TFTs), to solve crosstalk issues on the crossbar arrays. Here, an a-Indium-gallium-zinc-oxide (IGZO) memristor is proposed, with Mo and Ti/Mo as bottom and top contacts, with forming-free analog switching ability for an upcoming integration on crossbar arrays with a-IGZO TFTs for neuromorphic hardware systems. The development of a TFT compatible fabrication process is accomplished, which results in an a-IGZO memristor with a high stability and low cycle-to-cycle variability. The synaptic behavior through potentiation and depression tests using an identical spiking scheme is presented, and the modulation of the plasticity characteristics by applying non-identical spiking schemes is also demonstrated. The pattern recognition accuracy, using MNIST handwritten digits dataset, reveals a maximum of 91.82% accuracy, which is a promising result for crossbar implementation. The results displayed here reveal the potential of Mo/a-IGZO/Ti/Mo memristors for neuromorphic hardware.

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.

Neuromorphic hardware systems have been gaining ever-increasing focus in many embedded applications as they use a brain-inspired, energy-efficient spiking neural network (SNN) model that closely mimics the human cortex mechanism by communicating and processing sensory information via spatiotemporally sparse spikes. In this paper, we fully leverage the characteristics of spiking convolution neural network (SCNN), and propose a scalable, cost-efficient, and high-speed VLSI architecture to accelerate deep SCNN inference for real-time low-cost embedded scenarios. We leverage the snapshot of binary spike maps at each time-step, to decompose the SCNN operations into a series of regular and simple time-step CNN-like processing to reduce hardware resource consumption. Moreover, our hardware architecture achieves high throughput by employing a pixel stream processing mechanism and fine-grained data pipelines. Our Zynq-7045 FPGA prototype reached a high processing speed of 1250 frames/s and high recognition accuracies on the MNIST and Fashion-MNIST image datasets, demonstrating the plausibility of our SCNN hardware architecture for many embedded applications.

Research on the Robustness Mechanism of Maeda–Makino Hardware Neuron Based on Symbolic Dynamics

Noise permeates every level of the nervous systems, from single neurons to the whole system. However, the noise seems not to take so much trouble to neural information processing in contrast to the electronic system. The robustness of neural information processing inspired us to study the method of neuromorphic hardware systems to resist electromagnetic interference. The dynamics of the neuron model can reflect the inherent mechanism of neural information processing. In this work, we take the Maeda-Makino (MM) hardware neuron as an example to study the robustness mechanism of biological neuron information encoding based on symbolic dynamics. MM hardware neuron is a neuromorphic neuron circuit with biological plausibility. The simulation results show that MM hardware neuron can encode the order of current stimulus periods, even with parameter disturbance and noisy input signals which simulate the effects of electromagnetic interference on neuronal cell membrane permeability, sodium ion channels, potassium ion channels, and action potentials. Choosing a robust hardware neuron is the basis for building a neuromorphic hardware system that can resist electromagnetic interference. This letter not only verifies the robustness of using symbol sequence encoding but also provides an optional hardware neuron solution for neuromorphic hardware designed for anti-electromagnetic interference.