A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.

Ling Zhang,Liyuan Liu,Wei He,Nanjian Wu,Cong Shi,Yingcheng Lin,Jing Yang,Xichuan Zhou,Xu Yang

doi:10.3390/s21186006

Abstract

Neuromorphic hardware systems have been gaining ever-increasing focus in many embedded applications as they use a brain-inspired, energy-efficient spiking neural network (SNN) model that closely mimics the human cortex mechanism by communicating and processing sensory information via spatiotemporally sparse spikes. In this paper, we fully leverage the characteristics of spiking convolution neural network (SCNN), and propose a scalable, cost-efficient, and high-speed VLSI architecture to accelerate deep SCNN inference for real-time low-cost embedded scenarios. We leverage the snapshot of binary spike maps at each time-step, to decompose the SCNN operations into a series of regular and simple time-step CNN-like processing to reduce hardware resource consumption. Moreover, our hardware architecture achieves high throughput by employing a pixel stream processing mechanism and fine-grained data pipelines. Our Zynq-7045 FPGA prototype reached a high processing speed of 1250 frames/s and high recognition accuracies on the MNIST and Fashion-MNIST image datasets, demonstrating the plausibility of our SCNN hardware architecture for many embedded applications.

Highlights

Neuromorphic computing has attracted ever-increasing interest in the past ten years
The main contributions of our work include: (1) this paper proposes a scalable, highspeed and low-cost neuromorphic VLSI architecture for spiking convolution neural network (SCNN) inference in real-time and resource-constrained application scenarios; (2) we leverage the snapshot of binary spike maps at each time-step along with the spike-map pixel stream processing pipeline to maximize spike throughput, while minimizing the computation and storage consumptions of hardware resources; (3) this architecture was prototyped on an FPGA platform with different SCNN depth configurations
We used the SystemVerilog to describe the proposed SCNN hardware architecture and the processing circuits prototyped on a Xilinx Zynq-7045 FPGA chip

Summary

Introduction

Neuromorphic computing has attracted ever-increasing interest in the past ten years. The spiking neural network (SNN) closely mimics the operational mechanism in the human brain cortex, where information is encoded, communicated, and processed via very sparse electrical pulses (i.e., spikes) among neurons, ensuring high-energy efficiency in cognitive tasks [1]. ANNs employ dense computations and all of the neurons have to participate in an inference, while SNNs leverage temporally sparse spike trains and may activate only a small portion of neurons during the inference. Another difference is that SNNs require a time dimension to evolve with the temporal spike trains. General-purpose computers such as the Central Processing Unit (CPU) and the Graphics Processing Unit (GPU) are incompetent in deploying brain-inspired SNN models, as those von Neumann machines are oriented for dense numerical calculations rather than sparse temporal spike processing

Results

Discussion

Conclusion