Neural Chip Research Articles

PASS: Patch Automatic Skip Scheme for Efficient On-Device Video Perception.

Real-time video perception tasks are often challenging on resource-constrained edge devices due to the issues of accuracy drop and hardware overhead, where saving computations is the key to performance improvement. Existing methods either rely on domain-specific neural chips or priorly searched models, which require specialized optimization according to different task properties. These limitations motivate us to design a general and task-independent methodology, called Patch Automatic Skip Scheme (PASS), which supports diverse video perception settings by decoupling acceleration and tasks. The gist is to capture inter-frame correlations and skip redundant computations at patch level, where the patch is a non-overlapping square block in visual. PASS equips each convolution layer with a learnable gate to selectively determine which patches could be safely skipped without degrading model accuracy. Specifically, we are the first to construct a self-supervisory procedure for gate optimization, which learns to extract contrastive representations from frame sequences. The pre-trained gates can serve as plug-and-play modules to implement patch-skippable neural backbones, and automatically generate proper skip strategy to accelerate different video-based downstream tasks, e.g., outperforming state-of-the-art MobileHumanPose in 3D pose estimation and FairMOT in multiple object tracking, by up to 9.43 × and 12.19 × speedups, respectively, on NVIDIA Jetson Nano devices.

Synaptic plasticity and memory mimicked in solution-processed K-doped CuI thin film transistors

Low-voltage electric double layer p-type thin film transistors (TFTs) were fabricated on glass substrates with copper iodide doped with potassium iodide (Cu0.95K0.05Ix) as the channel and chitosan as the dielectric. Cu0.95K0.05Ix TFTs exhibited Ion/Ioff ratio of 2.5 × 104, subthreshold swing of 30 mV/dec, threshold voltage of 1.34 V, operating voltage of 2 V, and saturation field-effect mobility of 16.6 cm2 V−1 s−1. The relaxation phenomenon induced by ion migration was effectively utilized, enabling Cu0.95K0.05Ix TFTs to simulate various synaptic plasticity functions. When a pulse is applied, the drain current reaches a peak, but it takes more time for the current to return to its equilibrium position after the pulse is removed, demonstrating the short-term memory (STM) characteristics of Cu0.95K0.05Ix TFT. It was observed an increasing trend in excitatory postsynaptic current (EPSC) with enhanced pulse width and amplitude, and when the pulse amplitude increased to −10 V, the TFT transitioned from STM to long-term memory characteristics. Furthermore, the measurement of consecutive EPSC revealed the paired-pulse facilitation (PPF) characteristics, with a gradual decrease in the PPF coefficient as the time interval increased, and a selective stronger response to high-frequency signals. Based on the aforementioned research, by extending the device structure to a dual in-plane-gate structure configuration and applying different pulse voltage sequences on the dual gate, the NOR logic functionality was achieved. The study demonstrates the significant potential of p-type Cu0.95K0.05Ix TFTs in the field of synaptic bionics, simulating human learning and memory, and neural chips.

A Simple Nonlinear Classifier Using a Multimode Optical Chip

Neural network accelerator based on photonic‐integrated circuits is emerging as a promising technology for fast, power‐efficient, and parallel computing. Under such technology, optics is mainly used for linear transformations, e.g., through an array of cascaded switching networks. Nonlinear activation is implemented either electronically requiring extra optical–electrical conversion or via nonlinear optical materials that often suffer from high loss, large power consumption, and difficulty in integration. Herein, an optical neural chip with only one multimode waveguide, fabricated using low‐cost linear optical materials, plus seven heater electrodes to control the multimode interference, is proposed. The nonlinear networks are intrinsically integrated in the electrical‐to‐optical signal conversion through the waveguide. The linear computation, in the electronic domain, is included in the mandatory step to convert the input matrix to the intermediate current values on the seven electrodes. Though extremely simple, the proposed system can classify nonlinear datasets and images by optical readout with high accuracy and without calibration. Prospects for future development are given at the end. In this work, an alternative route is offered to exploiting the classic multimode interference for advanced optical computing applications.

Microdisk modulator-assisted optical nonlinear activation functions for photonic neural networks

On-chip implementation of optical nonlinear activation functions (NAFs) is essential for realizing large-scale photonic neural chips. To improve the reconfigurability and enrich the functions of photonic neural network (PNN), an NAF unit with a unique capability of performing multiple types of NAFs is highly preferred. In this work, we propose and experimentally demonstrate a microdisk modulator (MDM)-assisted NAF unit, in which multiple types of electro-optic NAFs with a high response speed and multiple types of all-optical NAFs with a low latency and reduced power consumption are performed in a single device. The fabricated MDM has an add-drop configuration, in which a lateral PN junction is incorporated to achieve high-speed resonance wavelength tuning. With the use of the high-speed nonlinear electro-optic effect, three different kinds of electro-optic NAFs including sigmoid function, radial basis function (RBF), and negative rectified linear unit (ReLU) function are realized by exploiting the free-carrier dispersion effect on silicon. Moreover, thanks to the strong optical confinement in the disk cavity, all-optical NAFs can be performed by exploiting the thermo-optic effect on silicon. In the experiment, four different kinds of all-optical NAFs including softplus function, RBF, clamped ReLU function, and leaky ReLU function are demonstrated. With the use of the realized clamped ReLU function, a convolutional neural network is simulated to perform a handwritten digit classification benchmark task, and an accuracy as high as 98 % is demonstrated. Thanks to its strong electro-optic and thermo-optic effects, the proposed MDM provides a unique capability of performing multiple types of electro-optic and all-optical NAFs, which is potential to be served as a flexible nonlinear unit in large-scale PNN chips.

PASS: Patch Automatic Skip Scheme for Efficient Real-Time Video Perception on Edge Devices

Real-time video perception tasks are often challenging over the resource-constrained edge devices due to the concerns of accuracy drop and hardware overhead, where saving computations is the key to performance improvement. Existing methods either rely on domain-specific neural chips or priorly searched models, which require specialized optimization according to different task properties. In this work, we propose a general and task-independent Patch Automatic Skip Scheme (PASS), a novel end-to-end learning pipeline to support diverse video perception settings by decoupling acceleration and tasks. The gist is to capture the temporal similarity across video frames and skip the redundant computations at patch level, where the patch is a non-overlapping square block in visual. PASS equips each convolution layer with a learnable gate to selectively determine which patches could be safely skipped without degrading model accuracy. As to each layer, a desired gate needs to make flexible skip decisions based on intermediate features without any annotations, which cannot be achieved by conventional supervised learning paradigm. To address this challenge, we are the first to construct a tough self-supervisory procedure for optimizing these gates, which learns to extract contrastive representation, i.e., distinguishing similarity and difference, from frame sequence. These high-capacity gates can serve as a plug-and-play module for convolutional neural network (CNN) backbones to implement patch-skippable architectures, and automatically generate proper skip strategy to accelerate different video-based downstream tasks, e.g., outperforming the state-of-the-art MobileHumanPose (MHP) in 3D pose estimation and FairMOT in multiple object tracking, by up to 9.43 times and 12.19 times speedups, respectively. By directly processing the raw data of frames, PASS can generalize to real-time video streams on commodity edge devices, e.g., NVIDIA Jetson Nano, with efficient performance in realistic deployment.

Towards Strong AI with Analog Neural Chips

Applied AI chips with neural networks fail to capture and scale different forms of human intelligence. In this study, the definition of a strong AI system in hardware and architecture for building neuro memristive strong AI chips is proposed. The architecture unit consists of loop and hoop networks that are built on recurrent and feed forward information propagation concepts. Applying the principle that ’every brain is different’; we build a strong network that can take different structural and functional forms. The strong networks are building using hybrids of loop and hoop networks having generalization abilities, with higher levels of randomness incorporated to introduce greater flexibility in creating different neural architectures.

A 218 GOPS neural network accelerator based on a novel cost-efficient surrogate gradient scheme for pattern classification

The accuracy and hardware efficiency of a neural system depends critically on the choice of an activation function. Rectified linear unit (ReLU) is a contemporary activation function that yields high accuracy and allows the construction of efficient neural chips, but it results in a lot of dead neurons, especially at the output layer. This problem is more pronounced in case of multichannel, multiclass classification. This is due to the fact that ReLU cancels out negative values altogether, as a result of which the corresponding values cannot be successfully backpropagated. This phenomenon is referred to as the dying ReLU problem. In this article, we present a novel ‘surrogate gradient’ learning scheme in order to solve gradient vanishing and the dying ReLU problems. To the best of our knowledge, this is the first learning scheme that enables the use of ReLU for all network layers while solving the Dying ReLU problem. We also present a high-performance inference engine that uses ReLU-based actuators for all the network layers in order to achieve high hardware efficiency. The design is excellent for online learning as well, since the derivative of the activation is equal to a constant and can be implemented using low-complexity components. The proposed technique significantly outperforms various contemporary schemes for the CIFAR-10 dataset, and can successfully yield about 98.39% accuracy on MNIST dataset while using less than 159k synapses. Moreover, the proposed hardware implementation is able to perform about 218 giga operation per second (GOPS) while consuming only about 3.95 slice registers and 25.89 slice look-up tables per synapse on a low-end Virtex 6 FPGA. The system is able to operate at a clock frequency of 93.2 MHz.

Planar Multi-Gate Artificial Synaptic Transistor with Solution-Processed AlOx Solid Electric Double Layer Dielectric and InOx Channel

Multi-terminal artificial synaptic devices are promising for building neural morphological networks and manufacturing neural chips. In this study, planar multi-gate InOx-based artificial synaptic transistor was demonstrated by using solution-processed AlOx as an electric double layer (EDL) dielectric with mobile hydrogen protons. The excitatory postsynaptic current (EPSC) was successfully controlled by adjusting amplitude, duration, and interval of the stimulating voltage pulses applied on the planar gates. The EPSC stimulated by multiple inputs shows the property of sublinear summation. As spatial resolution function of the artificial synaptic transistor, the EPSC depends on the presynaptic (planar gate) area and distance to the channel, nonlinearly. The paired-pulse facilitation (PPF), depending on time sequence, demonstrates the temporal resolution function of the multi-gate artificial synaptic transistor. The study shows the potential of planar multi-gate AlOx/InOx EDL transistor as multi-terminal artificial synaptic device.

Recent Progress and Perspectives on Neural Chip Platforms Integrating PDMS-Based Microfluidic Devices and Microelectrode Arrays.

Recent years have witnessed a spurt of progress in the application of the encoding and decoding of neural activities to drug screening, diseases diagnosis, and brain-computer interactions. To overcome the constraints of the complexity of the brain and the ethical considerations of in vivo research, neural chip platforms integrating microfluidic devices and microelectrode arrays have been raised, which can not only customize growth paths for neurons in vitro but also monitor and modulate the specialized neural networks grown on chips. Therefore, this article reviews the developmental history of chip platforms integrating microfluidic devices and microelectrode arrays. First, we review the design and application of advanced microelectrode arrays and microfluidic devices. After, we introduce the fabrication process of neural chip platforms. Finally, we highlight the recent progress on this type of chip platform as a research tool in the field of brain science and neuroscience, focusing on neuropharmacology, neurological diseases, and simplified brain models. This is a detailed and comprehensive review of neural chip platforms. This work aims to fulfill the following three goals: (1) summarize the latest design patterns and fabrication schemes of such platforms, providing a reference for the development of other new platforms; (2) generalize several important applications of chip platforms in the field of neurology, which will attract the attention of scientists in the field; and (3) propose the developmental direction of neural chip platforms integrating microfluidic devices and microelectrode arrays.

Neuralink - przymus czy możliwość? Stosunek państwa do „ulepszeń” na przykładzie implantów neuronowych

The development of technology such as neural chips prompts reflection on the state’s attitude to such and similar improvements, taking into account the legal possibilities of influencing citizens. The basis for considerations is the taxonomy of G.Cohen’s improvements and the standards of limiting rights and freedoms expressed in the ECtHR and the Polish Constitution. The aim of the article is to answer the following research question: do constitutional norms allow for the obligatory use of neural chips by citizens? The analysis was carried out both for the general public and selected social groups.The effect of the analysis has an impact on the future perception of the relationship between the state and the individual in connection with social changes resulting from the development of technology. The key to the presented and future considerations related to the place of improvement in the legal system is its impact on positional or absolute goods.

Scalable and compact photonic neural chip with low learning-capability-loss

Abstract Photonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for photonic matrix multiplier. It is desired to implement high-radix MZI mesh to boost the computation capability. Conventionally, three cascaded MZI meshes (two universal N × N unitary MZI mesh and one diagonal MZI mesh) are needed to express N × N weight matrix with O(N 2) MZIs requirements, which limits scalability seriously. Here, we propose a photonic matrix architecture using the real-part of one nonuniversal N × N unitary MZI mesh to represent the real-value matrix. In the applications like photonic neural network, it probable reduces the required MZIs to O(Nlog2 N) level while pay low cost on learning capability loss. Experimentally, we implement a 4 × 4 photonic neural chip and benchmark its performance in convolutional neural network for handwriting recognition task. Low learning-capability-loss is observed in our 4 × 4 chip compared to its counterpart based on conventional architecture using O(N 2) MZIs. While regarding the optical loss, chip size, power consumption, encoding error, our architecture exhibits all-round superiority.

A Charge Balanced Neural Stimulator Silicon Chip for Human-Machine Interface

This paper proposes a neural stimulator silicon chip design with an improved charge balancing technology. The proposed neural stimulation integrated circuit (IC) uses two charge balancing modules including synchronous charge detection module and short-time pulse insertion module. The synchronous charge detection module is designed based on a current splitter with ultra-small output current and an integrator circuit for neural stimulation pulse width control, which greatly reduces the residual charge remained on the electrode-tissue interface. The short-time pulse insertion module is designed based on the electrode voltage detection and compensation current control, which further reduces the accumulated residual charge and keeps the electrode voltage within a safety range of ±25 mV during multiple stimulation cycles. Finally, this neural stimulator is implemented in TSMC 0.18-μm CMOS process technology, and the chip function is tested and verified in both experiments with the electrode-tissue RC model and the PBS saline solution environment. The measurement result shows the neural stimulator chip achieves improved charge balancing with the residual charge smaller than 0.95 nC, which is the lowest compared to the traditional neural stimulator chips.

Application of a Memristive Neural Network for Classification of COVID-19 Patients

The global pandemic of COVID-19 has affected the lives of millions around the globe. We learn new facts about this corona virus every day. A contribution to this knowledge is described in the paper and it is related to employment of memristor neural networks and algorithms that help us analyze patients’ data and determine what patients are at increased risk for developing severe medical conditions once infected with the COVID-19. An efficient separation of potential patients in ill and healthy sub-groups is conducted using software and hardware neural networks, machine learning and unsupervised clustering. In the recent years, many works are related to reducing of neural chips area for the hardware realization of neural networks. For this purpose, a partial replacement of CMOS transistors in neural networks by memristors is made. Some of the main memristor advantages are its lower power consumption, nano-scale sizes, sound memory effect and a good compatibility to CMOS technology. In this reason, the main purpose of this paper is application of a memristor-based neural network with tantalum oxide memristor synapses for COVID-19 analysis. Additional experiments with data clustering are conducted. Experiments show that in fact patients with specific underlying health conditions and indicators are more predisposed to develop severe COVID-19 illness. This research is helpful for engineers and scientists to easier identifying patients that would need medical help

A Neural Recording and Stimulation Chip with Artifact Suppression for Biomedical Devices.

This paper presents chip implementation of the integrated neural recording and stimulation system with stimulation-induced artifact suppression. The implemented chip consists of low-power neural recording circuits, stimulation circuits, and action potential detection circuits. These circuits constitute a closed-loop simultaneous neural recording and stimulation system for biomedical devices, and a proposed artifact suppression technique is used in the system. Moreover, this paper also presents the measurement and experiment results of the implemented 4-to-4 channel neural recording and stimulation chip with 0.18 µm CMOS technology. The function and efficacy of simultaneous neural recording and stimulation is validated in both in vivo and animal experiments.

An optical neural chip for implementing complex-valued neural network

Complex-valued neural networks have many advantages over their real-valued counterparts. Conventional digital electronic computing platforms are incapable of executing truly complex-valued representations and operations. In contrast, optical computing platforms that encode information in both phase and magnitude can execute complex arithmetic by optical interference, offering significantly enhanced computational speed and energy efficiency. However, to date, most demonstrations of optical neural networks still only utilize conventional real-valued frameworks that are designed for digital computers, forfeiting many of the advantages of optical computing such as efficient complex-valued operations. In this article, we highlight an optical neural chip (ONC) that implements truly complex-valued neural networks. We benchmark the performance of our complex-valued ONC in four settings: simple Boolean tasks, species classification of an Iris dataset, classifying nonlinear datasets (Circle and Spiral), and handwriting recognition. Strong learning capabilities (i.e., high accuracy, fast convergence and the capability to construct nonlinear decision boundaries) are achieved by our complex-valued ONC compared to its real-valued counterpart.

Development of neural networks chip generating driving waveform for electrostatic motor

The authors are studying hardware neural networks (HNN) to control the locomotion of the microrobot. The neural networks chip is the integrated circuit chip of the HNN. We proposed the electrostatic motor that is the new actuator of the microrobot in our previous research. The electrostatic motor used the waveform generator to generate the driving waveform. In this paper, the authors will propose the driving circuit using neural networks chip. The cell body model is the basic component of the neural networks chip that outputs 3 MHz frequency of electrical oscillated pulse waveform. Therefore, large capacitors need to connect outside of the neural networks chip to generate the low-frequency driving waveform. The proposal neural networks chip generates a long delay without using large capacitors. In addition, the neural networks chip generated a two-phase anti-phase synchronized waveform by incorporating a mechanism for adjusting synaptic weight. As a result, the proposal neural networks chip can generate the electrostatic motor’s driving waveform with variable frequency. The frequency of the driving waveform could vary from 40 to 126 Hz.

Laser Beam‐Induced Transient Acoustic Waves in Graphene Oxides

Laser beam‐induced graphene oxides (GOs) with excellent tunable properties have to find attention in various applications. But, the understanding of the complex mechanics involved in this reduction process is incomplete, most primarily the reduction using ultrashort laser beam pulses. Herein, the influence of laser beam‐induced acoustic waves on the photoreduction as well as the generation of a reversible phase in the GOs using photoacoustic studies is presented. However, these waves influence the phase transition in GOs. These observations find aspiring applications for next‐generation optical technologies, such as data storage and neural chips.

Thermoplasmonic neural chip platform for in situ manipulation of neuronal connections in vitro

Cultured neuronal networks with a controlled structure have been widely studied as an in vitro model system to investigate the relationship between network structure and function. However, most cell culture techniques lack the ability to control network structures during cell cultivation, making it difficult to assess functional changes induced by specific structural changes. In this study, we present an in situ manipulation platform based on gold-nanorod-mediated thermoplasmonics to interrogate an in vitro network model. We find that it is possible to induce new neurite outgrowths, eliminate interconnecting neurites, and estimate functional relationships in matured neuronal networks. This method is expected to be useful for studying functional dynamics of neural networks under controlled structural changes.

Ai intelligent industrial design of Titan space probe (landing capsule and Saturn vehicle)

Exploring the solar system is of great significance for the realization of the community of human destiny. This article reviews the history of Saturn exploration and explores new directions in design aesthetics. The author designed a new type of Saturn’s sixth satellite (Titan) with three-dimensional software 3dsmax, including a landing capsule, a cruise vehicle (Saturn vehicle), involving the design of quantum communication, automatic driving, neural chain Ai chips, mechanical arms, etc. “Lack of beauty and tediousness”, pursue “characteristics, cultural innovation”. The new detector, with exquisite shapes and beautiful lines, combines the eastern cultural symbols of “Zhouyi and Dunhuang Feitian”, and uses memory metal and three-dimensional printing to manufacture, expanding the new Higgs boson, neutrino, and non-carbon-based life Explore the field, named “Hetu Jishu”, which closely combines mechanical aesthetics and the Silk Road.

A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors

Ultra low-power and high energy-efficient digital FIR filters and magnitude summation circuit are the key modules in spectral feature extraction (SFE) of portable thin-battery neural signal processing chips. A tailored SFE module design is presented in this brief. By adopting custom appropriate multiply-accumulate (MAC) circuits and novel ratioed logic style in custom standard cells’ design, the proposed SFE design is simplified with shorter logical path and faster subthreshold logic complex gates. Accuracy analysis is carried out to optimize the circuit structure with acceptable calculated results. Fabricated in 90 nm CMOS technology, the design has achieved 30% reduction of silicon area and 0.2 V lower supply voltage (hence over 50% elimination of power dissipation) in measurement, while compared to other regular works by standard design method. And the accuracy lost is within tolerant range.