Abstract
This paper presents chip implementation of the integrated neural recording and stimulation system with stimulation-induced artifact suppression. The implemented chip consists of low-power neural recording circuits, stimulation circuits, and action potential detection circuits. These circuits constitute a closed-loop simultaneous neural recording and stimulation system for biomedical devices, and a proposed artifact suppression technique is used in the system. Moreover, this paper also presents the measurement and experiment results of the implemented 4-to-4 channel neural recording and stimulation chip with 0.18 µm CMOS technology. The function and efficacy of simultaneous neural recording and stimulation is validated in both in vivo and animal experiments.
Highlights
Current flows through the tissue between two electrodes. erefore, the voltage variation emerges at the stimulation site near the working electrode due to its resistive and capacitive feature. e amplitude of this voltage variation usually ranges from a few hundred millivolts to a few volts, which is mainly determined by the current level and the electrode impedance [23,24,25,26]. en, the voltage waveform generated at the stimulation site has transmitted to the neural recording front end (RFE) through tissue, and it saturates the high-gain recording amplifier. e output signal from the saturated amplifier is called stimulationinduced artefact. e amplifier usually takes a long time to recover from this undesired saturation [23, 24]
To reduce the chip power consumption, the digitalto-analog converters (DACs) is powered by a 1.8 V supply, and the high-voltage current drivers (HVCD) is powered by 24 V. e output voltage compliance is large to deliver sufficient stimulation current. e reference voltage is set to a half VDD_h. e current amplitudes of both stimulation current generator (SCG) and countercurrent generator (CCG) are set by DACs and controlled by digital blocks
Bench-Top Measurement Results. e 4-to-4-channel closed-loop neural recording and stimulation system is implemented in 0.18-μm high-voltage CMOS technology with LDMOS option. e chip microphotograph is shown in Figure 7. e total chip area is 2 mm by 2 mm
Summary
2.1. 4-Channel Neural Recording and Stimulation Chip Implementation. A 4-channel neural recording and stimulation system is designed and presented in this work. E system consists of four-channel RFEs, four action potential detectors (APD), a global digital (DIG) control block, power down (PD) control, bandgap reference block (BGB) for biasing circuit, and four high-voltage artifact-suppressed stimulators (HVAS). E stimulation pulse width is determined by the timing control of the signals cathodic and anodic in high-voltage current drivers. E current amplitudes of both SCG and CCG are set by DACs and controlled by digital blocks. E trigger signal generated from APD is sent to the digital control block of the system which controls the stimulator With these two triggering signals from positive and negative threshold detectors, simple spike pattern recognition such as distinguishing biphasic spikes from electrical glitches is enabled. The current amplitude (D1′–D16′, D1–D16) of each step can be set by sending different commands to the DAC registers
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