Network-on-Chip Research Articles

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

Breaking On-Chip Communication Anonymity using Flow Correlation Attacks

Network-on-Chip (NoC) is widely used to facilitate communication between components in sophisticated System-on-Chip (SoC) designs. Security of the on-chip communication is crucial because exploiting any vulnerability in shared NoC would be a goldmine for an attacker that puts the entire computing infrastructure at risk. We investigate the security strength of existing anonymous routing protocols in NoC architectures, making two pivotal contributions. Firstly, we develop and perform a machine learning (ML)-based flow correlation attack on existing anonymous routing techniques in Network-on-Chip (NoC) systems, revealing that they provide only packet-level anonymity. Secondly, we propose a novel, lightweight anonymous routing protocol featuring outbound traffic tunneling and traffic obfuscation. This protocol is designed to provide robust defense against ML-based flow correlation attacks, ensuring both packet-level and flow-level anonymity. Experimental evaluation using both real and synthetic traffic demonstrates that our proposed attack successfully deanonymizes state-of-the-art anonymous routing in NoC architectures with high accuracy (up to 99%) for diverse traffic patterns. It also reveals that our lightweight anonymous routing protocol can defend against ML-based attacks with minor hardware and performance overhead.

Probability-based mapping approach for an application-aware networks-on-chip architectures

In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count. The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.

Neuron grouping and mapping methods for 2D-mesh NoC-based DNN accelerators

Deep Neural Networks (DNNs) have gained widespread adoption in various fields; however, their computational cost is often prohibitively high due to the large number of layers and neurons communicating with each other. Furthermore, DNNs can consume a significant amount of energy due to the large volume of data movement and computation they require. To address these challenges, there is a need for new architectures to accelerate DNNs. In this paper, we propose novel neuron grouping and mapping methods for 2D-mesh Network-on-Chip (NoC)-based DNN accelerators considering both fully connected and partially connected DNN models. We present Integer Linear Programming (ILP) and simulated annealing (SA)-based neuron grouping solutions with the objective of minimizing the total volume of data communication among the neuron groups. After determining a suitable graph representation of the DNN, we also apply ILP and SA methods to map the neurons onto a 2D-mesh NoC fabric with the objective of minimizing the total communication cost of the system. We conducted several experiments on various benchmarks and DNN models with different pruning ratios and achieved an average of 40-50% improvement in communication cost.

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing

Analog neuromorphic prototyping is essential for designing and testing spiking neuron models that use memristive devices as synapses. These prototypes can have various circuit configurations, implying different response behaviors that custom silicon designs lack. The prototype’s behavior results can be optimized for a specific foundry node, which can be used to produce a customized on-chip parallel deep neural network. Spiking neurons mimic how the biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. Therefore, on-chip parallel deep neural network technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging the neuromorphic hardware’s inherent parallelism and analog computation capabilities. This paper presents the design and implementation of a leaky integrate-and-fire (LIF) neuron prototype implemented with commercially available components on a PCB board. The simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be used to interconnect many boards to build layers of physical spiking neurons, with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting analog neuromorphic computing.

Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

Evaluation of genetic algorithm in network-on-chip based architecture

An increase in the number of cores gives a significant bounce in performance than an improvement in any of the factors or hardware. Many core systems use network-on-chip (NoC) for efficient communications among the cores in the system. However, the problem with NoC-based communication is that it significantly consumes a large amount of power and energy because the number of routers increases with the increase in the number of cores in the system. Power consumed by such components leads to degradation of the performance. The placement of cores in the topology is non-deterministic polynomial-time hardness (NP-Hard) problem. The optimal placement of cores in NoC is essential as it minimizes latency and communication costs. Thus, the NP-Hard problem of placing cores is solved using genetic algorithm (GA) based quadtree topology. The proposed work shows the analysis of GA-based quadtree topology, which outperforms other topologies in most aspects. The performance evaluation of GA-based quadtree topology is based on latency, throughput, power, area, bisection bandwidth, and diameter. Comparing these parameters with other topologies shows the prominence of the quadtree topology. The evaluation is performed in the Booksim simulator, and the experimental results revealed that the proposed GA-based quad tree-based topology is efficient for NoC-based communications.

Energy-aware task scheduling for streaming applications on NoC-based MPSoCs

Streaming applications are being extensively run on portable embedded systems, which are battery-operated and with limited memory. Thus, minimizing the total energy consumption of such a system is important. We investigate the problem of offline scheduling for streaming applications composed of non-preemptible periodic dependent tasks on homogeneous Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoCs) such that their total energy consumption is minimized under memory constraints. We propose a novel unified approach that integrates task-level software pipelining with Dynamic Voltage and Frequency Scaling (DVFS) to solve the problem. Our approach is supported by a set of novel techniques, which include constructing an initial schedule based on a list scheduling where the priority of each task is its approximate successor-tree-consistent deadline such that the workload across all the processors is balanced, a retiming heuristic to transform intra-period dependencies into inter-period dependencies for enhancing parallelism, assigning an optimal discrete frequency for each task and each message using a Non-Linear Programming (NLP)-based algorithm and an Integer-Linear Programming (ILP)-based algorithm, and an incremental approach to reduce the memory usage of the retimed schedule in case of memory size violations. Using a set of real and synthetic benchmarks, we have implemented and compared our unified approach with two state-of-the-art approaches, RDAG+GeneS (Wang et al., 2011) , and JCCTS (Wang et al., 2013a). Experimental results show that our approach’s maximum, average, and minimum improvements over RDAG+GeneS (Wang et al., 2011) are 31.72%, 14.05%, and 7.00%, respectively. Our approach’s maximum, average, and minimum improvement over JCCTS (Wang et al., 2013a) are 35.58%, 17.04%, and 8.21%, respectively.

Deep multiband photodetectors enabled by reconfigurable band alignment in van der Waals heterostructures

Multiband recognition technology is being extensively investigated because of the increasing demand for on-chip, multifunctional, and sensitive devices that can distinguish coincident spectral information. Most existing multiband imagers use large arrays of photodetectors to capture different spectral components, from which their spectrum is reconstructed. A single device embedded with a convolutional neural network (CNN) capable of recognizing multiband photons allows the footprints of multiband recognition chips to be scaled down while achieving spectral resolution approaching that of benchtop systems. Here, we report a multiple and broadband photodetector based on 2D/3D van der Waals p/n/p heterostructures [p-germanium (Ge)/n-molybdenum disulfide (MoS2)/p-black phosphorus (bP)] with an electrically tunable transport-mediated spectral photoresponse. The devices show bias-tunable multiband photodetection (visible, short-wave infrared, and mid-wave infrared photoresponse). Further combination with the CNN algorithm enables crosstalk suppression of photoresponse to different wavelengths and high-accuracy blackbody radiation temperature recognition. The deep multiband photodetection strategies demonstrated in this work may open pathways towards the integration of multiband vision for application in on-chip neural network perception.

Hardware Compression Method for On-Chip and Interprocessor Networks with Wide Channels and Wormhole Flow Control Policy

Increasing the number of processing cores is currently a common way to boost processor performance. However, the load on the memory subsystem consequently increases as the number of its agents grows. Hardware data compression is an unconventional approach to improving memory subsystem performance by reducing, firstly, the main memory access rate by increasing the cache capacity and, secondly, data traffic by packing the data more densely. The paper describes the implementation of hardware data compression in the on-chip network and interprocessor links of a configuration with wide data transmission channels and a wormhole flow control policy. The existing solutions cannot be applied to such configurations because they are essentially based on using narrow data channels and flow control policies implying uninterrupted packet transmission, which is not maintained with the wormhole flow control. The method proposed in this paper enables the use of hardware compression in the aforementioned configuration by moving data compression and decompression from networks to the connected devices, as well as by using a number of optimizations to hide the data processing delays. Optimizations of some specific cases, such as the transmission of large data packets with several cache lines or the transmission of zero data, are considered. Special attention is given to data transmission via interprocessor links, where, due to their lower bandwidth compared to the on-chip network, data compression can be the most beneficial. The increase in memory subsystem bandwidth from using hardware data compression was confirmed in the experiments showing the relative IPC increase in SPEC CPU2017 benchmarks up to 14 percent.

Network on Chip and Its Low Power Techniques

The advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques. Key Words: Network-On-Chip, System-On-Chip, latency and scalability

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

OpSAVE: Eviction Based Scheme for Efficient Optical Network-on-Chip

For on-chip networks, nanophotonics has been considered a strong alternative owing to its high speed (due to low latency) and high bandwidth (due to wavelength division multiplexing). However, the major hurdle in the adoption of nanophotonic-based on-chip networks is their high static power consumption. Various proposals are there in the literature which try to reduce the static power consumption either by modulating the laser or by allowing the on-chip stations to share the photonic channels. In this paper, we propose OpSAVE— an optical NoC that combines the above two strategies to effectively reduce static power consumption. It proposes a superior prediction mechanism based on the eviction details from the private caches. It explains how shared channels can be used to dynamically balance the load and at the same time handle mispredictions. It allows the optical stations to share both the power and the available bandwidth to increase their utilization. Moreover, OpSAVE proposes to use a double pumping strategy to improve the system performance. We compared our scheme with the state-of-the-art proposals in this domain and the results show that our scheme consumes 4.4X less optical power and at the same time improves the performance by nearly 28%. In the evaluation, we have considered the multicore benchmarks from the Splash and Parsec benchmark suites.

Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm

In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems.

Ultra-Wideband Transformer Feedback Monolithic Microwave Integrated Circuit Power Amplifier Design on 0.25 μm GaN Process.

This paper presents an ultra-wideband transformer feedback (TFB) monolithic microwave integrated circuit (MMIC) power amplifier (PA) developed using a 0.25 μm gallium nitride (GaN) process. To broaden the bandwidth, a drain-to-gate TFB technique is employed in this PA design, achieving a 117% relative -3 dB bandwidth, extending from 5.4 GHz to 20.3 GHz. At a 28 V supply, the designed PA circuit achieves an output power of 25.5 dBm and a 14 dB small-signal gain in the frequency range of 6 to 19 GHz. Within the 6 to 19 GHz frequency range, the small-signal gain exhibits a flatness of less than 0.78 dB. The PA chip occupies an area of 1.571 mm2. This work is the first to design a power amplifier with on-chip transformer feedback in a compound semiconductor MMIC process, and it enables the use of the widest bandwidth power amplifier on-chip transformer matching network.

HybMED: A Hybrid Neural Network Training Processor with Multi-Sparsity Exploitation for Internet of Medical Things.

Cloud-based training and edge-based inference modes for Artificial Intelligence of Medical Things (AIoMT) applications suffer from accuracy degradation due to physiological signal variations among patients. On-chip learning can overcome this issue by online adaptation of neural network parameters for user-specific tasks. However, existing on-chip learning processors have limitations in terms of versatility, resource utilization, and energy efficiency. We propose HybMED, which is a novel neural signal processor that supports on-chip hybrid neural network training using a composite direct feedback alignment-based paradigm. HybMED is suitable for general-purpose health monitoring AIoMT devices. It improves resource utilization and area efficiency by the reconfigurable homogeneous core with heterogeneous data flow and enhances energy efficiency by exploiting sparsity at different granularities. The chip was fabricated by TSMC 40nm process and tested in multiple physiological signal processing tasks, demonstrating an average improvement in accuracy of 41.16% following online few-shot learning. The chip demonstrates an area efficiency of 1.17 GOPS/mm2 and an energy efficiency of 1.58 TOPS/W. Compared to the previous state-of-the-art physiological signal processors with on-chip learning, the chip achieves a 65× improvement in area efficiency and 1.48× improvement in energy efficiency, respectively.

Energy-aware application mapping methods for mesh-based hybrid wireless network-on-chips

The 2D mesh topology-based Network-on-Chip (NoC) is a prevalent structure in System-on-Chip (SoC) designs, offering implementation and fabrication benefits. However, increased NoC scale leads to longer communication paths, more hops, and higher end-to-end latency and energy consumption. To mitigate these issues, Wireless NoC (WiNoC) integrates wireless communication, enhancing data rates, energy efficiency, and routing flexibility. Despite several mapping algorithms for NoCs, optimal techniques for hybrid WiNoCs are underexplored. This study proposes two novel application mapping methods for 2D mesh topology-based hybrid WiNoCs, using quadratic programming (QP) and simulated annealing (SA). Our goal is to minimize communication-related energy consumption. We evaluated these methods across various wireless router configurations, benchmarks, and custom application graphs. The QP-based method excels in smaller problems, while the SA-based approach yields optimal or near-optimal results for larger sizes within practical runtimes.

Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design Study.

Visualization design studies bring together visualization researchers and domain experts to address yet unsolved data analysis challenges stemming from the needs of the domain experts. Typically, the visualization researchers lead the design study process and implementation of any visualization solutions. This setup leverages the visualization researchers' knowledge of methodology, design, and programming, but the availability to synchronize with the domain experts can hamper the design process. We consider an alternative setup where the domain experts take the lead in the design study, supported by the visualization experts. In this study, the domain experts are computer architecture experts who simulate and analyze novel computer chip designs. These chips rely on a Network-on-Chip (NOC) to connect components. The experts want to understand how the chip designs perform and what in the design led to their performance. To aid this analysis, we develop Vis4Mesh, a visualization system that provides spatial, temporal, and architectural context to simulated NOC behavior. Integration with an existing computer architecture visualization tool enables architects to perform deep-dives into specific architecture component behavior. We validate Vis4Mesh through a case study and a user study with computer architecture researchers. We reflect on our design and process, discussing advantages, disadvantages, and guidance for engaging in a domain expert-led design studies.