Network Hardware Research Articles

Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic Systems

Spiking neural networks are expected to bring high resources, power, and energy efficiency to machine learning hardware implementations. In this regard, they could facilitate the integration of Artificial Intelligence in highly constrained embedded systems, such as image classification in drones or satellites. If their logic resource efficiency is widely accepted in the literature, their energy efficiency still remains debated. In this article, a novel high-level metric is used to characterize the expected energy efficiency gain when using Spiking Neural Networks (SNN) instead of Formal Neural Networks (FNN) for hardware implementation: Synaptic Activity Ratio (SAR). This metric is applied to a selection of classification tasks including images and 1D signals. Moreover, a high-level estimator for logic resources, power usage, execution time, and energy is introduced for neural network hardware implementations on FPGA, based on four existing accelerator architectures covering both sequential and parallel implementation paradigms for both spiking and formal coding domains. This estimator is used to evaluate the reliability of the Synaptic Activity Ratio metric to characterize spiking neural network energy efficiency gain on the proposed dataset benchmark. This study led to the conclusion that spiking domain offers significant power and energy savings in sequential implementations. This study also shows that synaptic activity is a critical factor that must be taken into account when addressing low-energy systems.

An Approach to Recognize Vehicles Context Flow for Smartphone-Based Outdoor Parking Using Supervised Machine Learning Classifiers

Abstract— Finding an available parking space in outdoor environments such as university campuses and roadsides need a good parking system. In a general parking system, detecting a vehicle entering leaving the parking premise is one of the major steps. Currently, there are parking systems that use cameras or external sensors to detect the leaving and entering of the automobiles. External sensors-based systems require a costly sensor installation at each parking slot while the camera-based systems require sophisticated camera setup. Both parking systems need very high cost of deployment and maintenance. Besides, the additional need for network setup and hardware capacity increases the complexity that makes the system difficult to be implemented in an outdoor environment that typically involve a bigger coverage area. To encounter the issues, paper presents a parking system for outdoor parking systems using only smartphone-oriented sensors. The proposed approach does not require additional sensors installation nor manpower support. The proposed system takes the inputs from smartphones to detect the driver’s context that is used to recognize the flow of the vehicle. Context flow recognition indicates whether a driver is parking or unparking his/her vehicle. Supervised classifiers like support vector machines (SMV) and decision trees (DT) are used to recognize the parking or unparking actions to enable vehicles tracking in the parking area. Outcome of the proposed approach is a significant contribution for outdoor parking system as it solely utilizes the sensors embedded in smartphones to detect parking behaviors.

Feasibility Analysis and Implementation of Adaptive Dynamic Reconfiguration of CNN Accelerators

In multi-tasking scenarios with dynamically changing loads, the parallel computing of convolutional neural networks (CNNs) causes high energy and resource consumption in the system. Another critical problem is that previous neural network hardware accelerators are often limited to fixed scenarios and lack the function of adaptive adjustment. To solve these problems, a reconfiguration adaptive system based on the prediction of algorithm workload is proposed in this paper. Deep Learning Processor Unit (DPU) from Xilinx has excellent performance in accelerating network computing. After summarizing the characteristics of hardware accelerators and gaining an in-depth understanding of the DPU structure, we propose a regression model for CNNs runtime prediction and a guidance scheme for adaptive reconfiguration combined with the characteristics of Deep Learning Processor Unit. For different DPU sizes, the accuracy of the proposed prediction model achieves 90.7%. With the dynamic reconfiguration technology, the proposed strategy can enable accurate and fast reconfiguration. In the load change scenario, the proposed system can significantly reduce power consumption.

The Role and Impact of ICT in Improving the Quality of Education in Reference to NEP 2020

ICTs are making drastic changes in society. They are influencing all fields of life. Similarly, there is no doubt that ICT brings a enormous change in the field of education also. It makes teaching- learning process more effective and interesting. To know the impact of ICT in education we need to know two basic terms- ICT and education. The ICT is an umbrella that includes any communication device or application, encompassing, radio, television, cellular phones, computer, and network hardware and software, satellite system and so on, as well as the various services and applications associated with them, such as video conferencing and distance learning. Such technologies are used for educational purposes, namely to help and improve the learning of student and develop learning environments. ICT can be considered as a sub field of educational technology. The paper discusses the role and effect of ICTs, and how they can promote time ahead growth and development. In educational system, the inputs are teachers, students, classroom materials, equipment of teaching, methods of teaching and the outputs are quantity as well as quality of student learning result. The proper unification of ICT with teaching/ learning environment increases the chance of gaining education along with increased productivity. Information communication technologies are influencing all fields of life including education. They are promoting positive changes in working style, handling and exchanging of information, teaching- learning approaches . One area in which the impacts of ICT is significant, is education. ICTs are making major changes in the teaching approaches and the ways students are learning. ICT-based learning environment facilitates active, collaborative, creative, integrative, and evaluative learning as an advantage over the traditional method. In addition, the major advantages of ICTs use in education systems of developing countries focus on training teachers in new skills and introducing innovative pedagogies into the classrooms, investing on ICT infrastructure for schools and creating networks among educational institutes, improving overall standard of education by reducing the gap in quality of education between schools in urban and rural areas, initiation of smart school with objectives to foster self-paced, self-assessed, and self-directed learning through the applications of ICTs, and developing ICT policy for education and training.

Review of security issues in Internet of Things and artificial intelligence‐driven solutions

AbstractInternet of Things (IoT) is a network of several hardware and software systems which is broadly based upon internet services and several state‐of‐the‐art sensing and communication technologies. The emergence of 5G technology will witness a further surge in the growth of IoT across the world but simultaneously security concerns pertinent to the IoT technology also need rigorous evaluations. This article will present a thorough survey of the security challenges in an IoT network, recent cases of attacks on IoT technology, communication protocols prevalent in IoT systems and the role of artificial intelligence (AI) in IoT security. For the first time, all the major attributes related to IoT security along with potential solutions using AI are reviewed and articulated together. This work would act as a useful resource for understanding useful perspectives in future research focused around the development of more secured IoT communication protocols as well as AI tools for handling privacy and security in IoT.

Integration of Radar Sensing into Communications with Asynchronous Transceivers

Clock asynchronism is a critical issue in integrating radar sensing into communication networks. It can cause ranging ambiguity and prevent coherent processing of discontinuous measurements in integration with asynchronous transceivers. Should it be resolved, sensing can be efficiently realized in communication networks, requiring few network infrastructure and hardware changes. This article provides a systematic overview of existing and potential new techniques for tackling this fundamental problem. We first review existing solutions, including using a finetuned global reference clock, and single-node-based and network-based techniques. We then examine open problems and research opportunities, offering insights into what may be better realized in each of the three solution areas.

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs

In recent years, convolutional neural networks (CNNs) have achieved significant advancements in various fields. However, the computation and storage overheads of CNNs are overwhelming for Internet-of-Things devices. Both network pruning algorithms and hardware accelerators have been introduced to empower CNN inference at the edge. Network pruning algorithms reduce the size and computational cost of CNNs by regularizing unimportant weights to zeros. However, existing works lack intrakernel structured types to tradeoff between sparsity and hardware efficiency, and the index storage for irregularly pruned networks is significant. Hardware accelerators leverage the sparsity of pruned CNNs to improve energy efficiency. However, their process element (PE) utilization rate is low because of uneven sparsity among input convolutional kernels. To overcome these problems, we propose PACA: a Pattern pruning Algorithm and Channel-fused high PE utilization Accelerator for CNNs. It includes three parts: a pattern pruning algorithm to explore the intrakernel sparsity type and reduce the index storage, a channel-fused hardware architecture to reduce the PEs’ idle rate and improve the performance, and a heuristic and taboo search-based smart fusion scheduler to analyze the idle PE problem and schedule the channel fusion in hardware. To demonstrate the effectiveness of PACA, we have implemented the software parts by Python and the hardware architecture by RTL codes. Experimental results on various datasets show that compared with an existing work, PACA can reduce the index storage overhead by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.47\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.63\times $ </tex-math></inline-formula> with 3.85–9.12 average patterns, and it can improve the hardware performance by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.01\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.53\times $ </tex-math></inline-formula> because of PEs’ idle rate reduction.

ERDAC: Efficient and Reliable Remote Direct Access and Control for Embedded Systems

Emerging embedded systems, such as autonomous vehicles, demand highly efficient remote data transfer, whereas existing networking hardware and protocols cause high communication latency and CPU consumption. In this article, we propose embedded RDAC (eRDAC), an efficient and reliable remote direct access and control solution for embedded systems. The proposed remote access controller in eRDAC has a two-layer protocol offload engine that employs the command/response protocol on UDP to ensure the data reliability and security, and a multichannel DMA controller with configurable priority to improve the efficiency. Besides, a reusable hardware Ethernet MAC is implemented to support not only remote access commands but also standard Ethernet communication. We implement eRDAC on FPGA and the corresponding software in the Linux system. Experimental results show that eRDAC can reduce the latency of remote I/O reading/writing by 74.3%/74.9% ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.76\times /3.98\times $ </tex-math></inline-formula> performance improvement) and reduce the latency of remote memory reading and writing with 1024B by 54.2% compared to the socket-based communication. Meanwhile, eRDAC can cut off the consumption of the remote processor and achieve 0.250mJ/Mb energy consumption with only 25-mW power.

Design and Implementation of Dance Online Teaching System Based on Optimized Load Balancing Algorithm.

With the continuous improvement of the network hardware environment, people turn the demand target to the network application environment and the construction of information resources. How to build a network teaching platform for general undergraduate teaching to ensure the stability of the system and high-quality services during operation especially large-scale concurrent access will inevitably lead to the increase in the business volume of each core part of the network, the number of visits, and data traffic. With the growth of the network, the corresponding processing power and computing intensity also increase rapidly, which causes problems such as overloading of core network equipment, network bottlenecks, and network congestion. Simply pursuing high-performance hardware to solve problems will undoubtedly result in high cost investment; moreover, equipment with excellent performance cannot meet the needs of the current rapidly growing business volume. According to the design goal of the dance online teaching platform, to meet the online teaching load requirements of many people at the same time, the pressure of the web server cluster must be great. Because many people in online at the same time put too much pressure on the web server, this part of the network cannot be processed in time, which leads to the phenomenon that the performance of this part and even the whole network is degraded. In severe cases, it will even cause network communication services to come to a standstill, that is, the so-called deadlock phenomenon. If the protocol software cannot detect congestion and reduce the packet sending rate, the network will be paralyzed due to congestion. This situation will cause the problem of movement delay for online dance teaching, which will seriously affect the quality of teaching. Therefore, the dance online course system should be continuously improved, the quality of online courses should be continuously improved, and the study of the practical application of load balancing technology in the network teaching environment has become an important means to solve the relationship between supply and demand of network teaching. According to the experimental analysis, when the number of Worker' actuators is fixed, the execution time span of MakeSpan increases with the increase of tasks, while the time required by the optimized load balancing algorithm proposed in this paper increases by 1.32 s on average with the increase of tasks, and the time required by heuristic algorithm and bee colony algorithm increases by 3.68 s and 3.45 s on average with the increase of tasks. On the whole, the optimized load balancing algorithm proposed in this paper has obvious advantages.

Two-Neuron Based Memristive Hopfield Neural Network with Synaptic Crosstalk

Synaptic crosstalk is an important biological phenomenon that widely exists in neural networks. The crosstalk can influence the ability of neurons to control the synaptic weights, thereby causing rich dynamics of neural networks. Based on the crosstalk between synapses, this paper presents a novel two-neuron based memristive Hopfield neural network with a hyperbolic memristor emulating synaptic crosstalk. The dynamics of the neural networks with varying memristive parameters and crosstalk weights are analyzed via the phase portraits, time-domain waveforms, bifurcation diagrams, and basin of attraction. Complex phenomena, especially coexisting dynamics, chaos and transient chaos emerge in the neural network. Finally, the circuit simulation results verify the effectiveness of theoretical analyses and mathematical simulation and further illustrate the feasibility of the two-neuron based memristive Hopfield neural network hardware.

Full-Inorganic Flexible Ag2S Memristor with Interface Resistance-Switching for Energy-Efficient Computing.

Flexible memristor-based neural network hardware is capable of implementing parallel computation within the memory units, thus holding great promise for fast and energy-efficient neuromorphic computing in flexible electronics. However, the current flexible memristor (FM) is mostly operated with a filamentary mechanism, which demands large energy consumption in both setting and computing. Herein, we report an Ag2S-based FM working with distinct interface resistance–switching (RS) mechanism. In direct contrast to conventional filamentary memristors, RS in this Ag2S device is facilitated by the space charge-induced Schottky barrier modification at the Ag/Ag2S interface, which can be achieved with the setting voltage below the threshold voltage required for filament formation. The memristor based on interface RS exhibits 105 endurance cycles and 104 s retention under bending condition, and multiple level conductive states with exceptional tunability and stability. Since interface RS does not require the formation of a continuous Ag filament via Ag+ ion reduction, it can achieve an ultralow switching energy of ∼0.2 fJ. Furthermore, a hardware-based image processing with a software-comparable computing accuracy is demonstrated using the flexible Ag2S memristor array. And the image processing with interface RS indeed consumes 2 orders of magnitude lower power than that with filamentary RS on the same hardware. This study demonstrates a new resistance–switching mechanism for energy-efficient flexible neural network hardware.

Flexible Active Crossbar Arrays Using Amorphous Oxide Semiconductor Technology toward Artificial Neural Networks Hardware

AbstractMemristor crossbar arrays can compose the efficient hardware for artificial intelligent applications. However, the requirements for a linear and symmetric synaptic weight update and low cycle‐to‐cycle (C2C) and device‐to‐device variability as well as the sneak‐path current issue have been delaying its further development. This study reports on a thin‐film amorphous oxide‐based 4×4 1‐transistor 1‐memristor (1T1M) crossbar. The a‐IGZO crossbar is built on a flexible polyimide substrate, enabling IoT and wearable applications. In the novel framework, the thin‐film transistor and memristor are fabricated at the same level, with the same processing steps and sharing the same materials for all layers. The 1T1M cells show linear and symmetrical plasticity characteristic with low C2C variability. The memristor performs like an analog dot product engine and vector–matrix multiplications in the 4×4 crossbars is demonstrated experimentally, in which the sneak‐path current issue is successfully suppressed, resulting in a proof‐of‐concept for a cost‐effective, flexible artificial neural networks hardware.

Exploiting Read Current Noise of TiOx Resistive Memory by Controlling Forming Conditions for Probabilistic Neural Network Hardware

Conductance variations of resistive random-access memory (RRAM) are significant challenges that hinder the accurate inference of neural network (NN) hardware. In this study, we exploit the read noise of the RRAM as an active computational enabler for implementing probabilistic NN. As electrical characteristics of RRAM are directly related to the properties of conductive filament (CF), we statistically explore read current of TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based RRAM with different forming conditions and explain the results by linking the CF model. In addition, an array mapping scheme to transfer weights to one transistor-one RRAM (1T1R) array is experimentally demonstrated. Through NN simulations, we verify that the probabilistic NN shows promising results on nonlinear classification problem avoiding overconfidence compared with deterministic NN.

Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators

Deep neural network (DNN) hardware accelerators are being deployed widely to accelerate the inference process. Security of such accelerators is a major challenge, especially when being deployed in safety-critical systems such as autonomous vehicles. In this letter, we present novel Hardware Trojan (HT) attacks on two DNN hardware accelerators, which modifies the activation parameters of the DNN in a field-programmable gate array-based accelerator implementation. The proposed HT is agnostic to the detailed architecture of the DNN. Experimental results demonstrate that the proposed HT is extremely stealthy, and when activated can result in significant degradation in inference accuracy.

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks

Multi-bit-width convolutional neural network (CNN) maintains the balance between network accuracy and hardware efficiency, thus enlightening a promising method for accurate yet energy-efficient edge computing. In this work, we develop state-of-the-art multi-bit-width accelerator for NAS Optimized deep learning neural networks. To efficiently process the multi-bit-width network inferencing, multi-level optimizations have been proposed. Firstly, differential Neural Architecture Search (NAS) method is adopted for the high accuracy multi-bit-width network generation. Secondly, hybrid Booth based multi-bit-width multiply-add-accumulation (MAC) unit is developed for data processing. Thirdly, vector systolic array is proposed for effectively accelerating the matrix multiplications. With vector-style systolic dataflow, both the processing time and logic resources consumption can be reduced when compared with the classical systolic array. Finally, The proposed multi-bit-width CNN acceleration scheme has been practically deployed on FPGA platform of Xilinx ZCU102. Average performance on accelerating the full NAS optimized VGG16 network is 784.2 GOPS, and peek performance of the convolutional layer can reach as high as 871.26 GOPS for INT8, 1676.96 GOPS for INT4, and 2863.29 GOPS for INT2 respectively, which is among the best results in previous CNN accelerator benchmarks.

Mechanical Vibration Test Based on the Wireless Vibration Monitoring System

In order to apply wireless sensor networks to mechanical vibration monitoring, the author proposes a wireless network topology with multiple data collection points for mechanical vibration monitoring. This structure reduces the transmission load of the data collection point, increases the data transmission rate of the network, balances the energy dissipation in the network, and utilizes the general wireless sensor network hardware platform. The network transmission protocol and related auxiliary mechanisms are designed and implemented, and a wireless vibration monitoring test platform is constructed. The transmission performance of the network structure with multiple data collection points is evaluated through the actual test. The experimental results show that by using the wireless sensor network topology with multiple data collection points, it can meet the requirements of continuous transmission of vibration data obtained by 1 kHz sampling. Conclusion. The system performance of the wireless sensor network based on this network structure has been improved under the condition of general hardware, and the network structure of multiple data collection points shows good performance in the process of high-speed data transmission.

Analysis of the Current Situation of Teaching and Learning of Ideological and Political Theory Courses by Deep Learning.

The objectives are to solve the problems existing in the current ideological and political theory courses, such as the difficulty of classroom teaching quality assessment, the confusion of teachers' classroom process management, and the lack of objective assessment basis in teaching quality monitoring. Based on Artificial Intelligence (AI) technology, a designed evaluation method is proposed for teachers' classroom teaching and solves some problems such as high system cost, low evaluation accuracy, and imperfect evaluation methods. Firstly, the boundary algorithm system is introduced in the research, and the Field Programmable Gate Array (FPGA) by deep learning (DL) is used to accelerate the server hardware network platform and equipped with pan tilt zoom (PTZ) and manage multiple AI + embedded visual boundary algorithm devices. Secondly, the network platform can manage the PTZ and focal length of Internet protocol (IP) cameras, measure, and capture face images, transmit data, and recognize students' face, head, and body postures. Finally, classroom teaching is evaluated, and students' behavioral data and functions are designed, debugged, and tested. The research results demonstrate that the method overcomes the problem of high system cost through edge computing and hardware structure, and DL technology is used to overcome the problem of low accuracy of classroom teaching evaluation. Various indicators such as attendance rate, concentration, activity, and richness of teaching links in classroom teaching are obtained. The method involved can make an objective evaluation of classroom teaching and overcome the problem of incomplete classroom teaching evaluation.

Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks

Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.

Multi‐objective evolutionary optimization for hardware‐aware neural network pruning

Neural network pruning is a popular approach to reducing the computational complexity of deep neural networks. In recent years, as growing evidence shows that conventional network pruning methods employ inappropriate proxy metrics, and as new types of hardware become increasingly available, hardware-aware network pruning that incorporates hardware characteristics in the loop of network pruning has gained growing attention. Both network accuracy and hardware efficiency (latency, memory consumption, etc.) are critical objectives to the success of network pruning, but the conflict between the multiple objectives makes it impossible to find a single optimal solution. Previous studies mostly convert the hardware-aware network pruning to optimization problems with a single objective. In this paper, we propose to solve the hardware-aware network pruning problem with Multi-Objective Evolutionary Algorithms (MOEAs). Specifically, we formulate the problem as a multi-objective optimization problem, and propose a novel memetic MOEA, namely HAMP, that combines an efficient portfolio-based selection and a surrogate-assisted local search, to solve it. Empirical studies demonstrate the potential of MOEAs in providing simultaneously a set of alternative solutions and the superiority of HAMP compared to the state-of-the-art hardware-aware network pruning method.

A methodology for assessing computation/communication overlap of MPI nonblocking collectives

A methodology for assessing computation/communication overlap of MPI nonblocking collectives