Negative Junction Depth Research Articles

Grooved-gate silicon-on-nothing (SON) MOSFET: evidence for suppressing SCEs

This paper presents a simulation-based systematic characterization of a dual-metal-stack grooved-step-gate (DMS-GSG) silicon-on-nothing (SON) metal–oxide–semiconductor field-effect transistor (MOSFET) with stack buried oxide (SBO) for restraining short-channel effects (SCEs). Comparison was done between silicon-on-insulator (SOI) and SON SBO grooved-gate (GG) MOSFETs to realize the feasibility of the presented structure. Analysis of thermal stability over a wide range of temperatures was carried out for better characterization of the proposed structure. Further, the impact of structural parameters such as the negative junction depth and the influence of the work-function difference on the threshold voltage, drain current and drain-induced barrier lowering were analyzed. The investigation revealed that the DMS-GSG SON MOSFET is more prominent than other GG SOI MOSFETs in terms of switching behavior, SCEs, hot-carrier effect, intrinsic gain and early voltage. Further, the presence of air in the SBO of the DMS-GSG SON MOSFET suppresses the self-heating effect. Thus, this in-depth investigation is relatively beneficial to find out the performance improvement of SON structures over SOI ones for nanoscale short-channel devices.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

Impact of structural parameters on DC performance of recessed channel SOI-MOSFET

With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a new analytical model is developed for the rectangular recessed channel silicon on insulator (RRC-SOI) metal oxide semiconductor field effect transistor (MOSFET). This analytical model is formulated using 2D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. This paper analyses the effect of negative junction depth (NJD) on device parameters, such as minimum surface potential, threshold voltage, sub-threshold slope (SS), and drain induced barrier lowering (DIBL). The impact of oxide thickness variation on the above parameters has also been evaluated. Further, the linearity performance in terms of figure of merits (FOM) and device parameters like drain current and trans-conductance of the proposed model is compared with the simulated results of rectangular recessed channel (RRC) MOSFET. The validity of the proposed model has been verified with simulation results performed on Sentaurus TCAD device simulator.

Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

AbstractThis paper attempts to propose a new device as workfunction modulated dual metal rectangular recessed channel silicon on insulator (WMDMRRC‐SOI) MOSFET. This model takes the advantage of recessed channel to reduce the hot‐carrier effect and a linear variation of workfunction at source side metal gate to achieve improved threshold voltage and electron transportation efficiency. The characteristics of WMDMRRC‐SOI MOSFET are analyzed in terms of electron behaviour like mobility, temperature, and velocity in the channel region. The impact of negative junction depth on threshold voltage and short‐channel effects like drain induced barrier lowering, subthreshold slope are analyzed to optimize the characteristics of the proposed architecture. Performance parameters of WMDMRRC‐SOI MOSFET are compared with the results of DMRRC‐SOI MOSFET and conventional RRC‐SOI MOSFET. The comparison interprets that with higher intrinsic gain and lower distortion, the proposed architecture gives better analog performance and enhanced short channel parameters. The results obtained are validated through Sentaurus TCAD device simulator.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson’s equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate length (LG) shrinking on analog and linearity performance of Transparent Gate Recessed Channel (TGRC) MOSFET with an aim to achieve a reliable and high performance transistor. It is found that device enhances the ION by 38% and thereby improves the analog performance in terms of transconductance, device efficiency, output resistance, and gain. Moreover, linearity figure of merits are also enhanced at lower gate bias in TGRC MOSFET in comparison to conventional and Conventional Recessed Channel (CRC) MOSFET due to reduced harmonic distortions (gm3). Thus, the improved analog and linearity performance at 5 nm NJD and 20 nm LG of TGRC-MOSFET makes it suitable for low power linear RF amplifiers as a nano-scaled device. Thus, these results would serve as a worthy design tool for low power and high performance CMOS circuits.

Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

This work discusses the capacitance–voltage (C–V) analysis and frequency dependent capacitance of In2O5Sn (Tin Oxide) gate electrode Recessed Channel (TGRC) MOSFET with an aim to examine the effectiveness of In2O5Sn (Transparent) as a gate material on parasitic capacitance which prominently influences the current driving capability and thus, the switching performance. Moreover, capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) are also assessed and found that, TFP increases to 6.33 times in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg = Cgs + Cgd), due to which EDP and GBP also improve considerably and thus reflects its effectiveness in RF amplifiers and receivers. In addition, the effect of parameter variation such as gate length (Lg) and negative junction depth (NJD) of TGRC is also observed, and results reveal that with Lg = 20 nm and NJD = 5 nm, TGRC unveils outstanding switching performance which is desirable for low power ULSI applications.

Effect of structured parameters on the hot-carrier immunity of transparent gate recessed channel (TGRC) MOSFET

In this work, the impact of parameter variation on hot-carrier effect immunity in transparent gate recessed channel (TGRC)—MOSFET based on the hydrodynamic energy transport model have been studied. The parameters of TGRC-MOSFET investigated include the oxide thickness, negative junction depth, and substrate doping. TCAD analysis shows the performance of TGRC-MOSFET in terms of transfer characteristics, transconductance, electric field, electron velocity, electron mobility and electron temperature. The simulation results indicate the improved hot-carrier immunity for TGRC-MOSFET in 30 nm device.

Power gain assessment of ITO based Transparent Gate Recessed Channel (TGRC) MOSFET for RF/wireless applications

In this work, power gain assessment and intrinsic delay of Transparent Gate Recessed Channel (TGRC) MOSFET have been observed for RF applications and the results so obtained have been compared with Conventional Recessed Channel (CRC) MOSFET. Simulation results show that TGRC architecture has significantly improved the power gains in terms of maximum available power gain (Gma), maximum transducer power gain (GMT), maximum stable power gain (Gms) and appreciable reduction in intrinsic delay as compared to CRC-MOSFET owing to indium tin oxide (ITO) in recessed channel as a conducting gate material and thus providing its efficacy for low power switching applications. Further, effect of gate length scaling has also been observed on TGRC MOSFET and it has been found that the cut-off frequency (fT) and maximum oscillator frequency (fMAX) enhances by 66% and 36% respectively as channel length scales down to 20 nm. Further, the effect of negative junction depth, oxide thickness and substrate doping have also been investigated for TGRC-MOSFET. This TCAD assessment has been done at frequencies of several THz which fortify its use for high frequency RF/wireless applications.

Enhanced I ON/I OFF in ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET

To manage the increasing static leakage in low power applications and reducing ON‐OFF current ratio due to scaling limitations, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. At the device design level, the important low power variables are the threshold voltage, the gate leakage current, the subthreshold leakage current and the device size. Grooved‐gate MOS devices are considered as the most promising candidates for use in submicron and deep submicron regions as they can overcome the short‐channel effects effectively. By varying the corner angle and adjusting other structural parameters such as junction depth, channel doping concentration, negative junction depth and oxide thickness, leakage current in nMOS devices can be minimised. In this article, 90, 80, 70, 60 and 50 nm devices are simulated using Devedit and Deckbuild module of Silvaco device simulator. The simulated results show that by changing the structural parameters, ON‐OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is drastically reduced, as well as applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this study.

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping ( N A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency ( f t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain ( Gma), maximum transducer power gain ( G MT), maximum unilateral power gain (MUG), maximum frequency of oscillation ( f MAX) and stern stability factor ( K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm<SUB>1</SUB>, gm<SUB>2</SUB>, gm<SUB>3</SUB>, and figure-of-merit (FOM) metrics; V<SUB>IP2</SUB>, V<SUB>IP3</SUB>, IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X<SUB>j</SUB>) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation

Part I of this paper dealt with the hot carrier reliability evaluation of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET involving channel recession and gate electrode workfunction engineering integration onto the conventional MOSFET, using an ATLAS device simulator. It was demonstrated that with the gate stack architecture incorporated onto the GEWE-RC MOSFET and tuning of various structural design parameters such as gate length ( L G ), negative junction depth (NJD), substrate doping ( N A ), gate metal workfunction, substrate bias ( V S U B ), drain bias ( V D S ) and gate oxide permittivity ( ε o x 2 ), excellent hot carrier immunity can be achieved in terms of conduction band offset, reduced electron velocity, electron temperature, hot electron injected gate current and impact ionization substrate current. This paper focuses on the analog and large signal performance metrics in terms of linearity, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design parameters such as L G , NJD, N A , gate metal workfunction and ε o x 2 for different substrate ( V S U B ) and drain to source ( V D S ) voltages. The work, thus, proves the effectiveness of GEWE-RC for RFICs with a higher efficiency, better linearity performance; and designing and modeling of power amplifiers.

Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

This paper discusses a threshold voltage model for novel device structure: gate electrode work function engineered recessed channel (GEWE-RC) nanoscale MOSFET, which combines the advantages of both RC and GEWE structures. In part I, the model accurately predicts (a) surface potential, (b) threshold voltage and (c) sub-threshold slope for single material gate recessed channel (SMG-RC) and GEWE-RC structures. Part II focuses on the development of compact analytical drain current model taking into account the transition regimes from sub-threshold to saturation. Furthermore, the drain conductance evaluation has also been obtained, reflecting relevance of the proposed device for analogue design. The analysis takes into account the effect of gate length and groove depth in order to develop a compact model suitable for device design. The analytical results predicted by the model confirm well with the simulated results. Results in part I also provide valuable design insights in the performance of nanoscale GEWE-RC MOSFET with optimum threshold voltage and negative junction depth (NJD), and hence serves as a tool to optimize important device and technological parameters for 40 nm technology.

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture&amp;#x2014;Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NA</i> ), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications

In this paper, an extensive study on the on-state, switching and RF performance of a laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET and the influence of technology variations such as gate length, negative junction depth (NJD) and gate bias on the device's behavior is performed using an ATLAS device simulator. Simulations reveal that the L-DUMGAC design exhibits a significant enhancement in the device's switching characteristics in terms of reduced on-resistance and, hence, the reduced conduction power loss, switching loss and enhanced on-current, ION. Further, the L-DUMGAC design is studied for the RF application circuit design by examining the stability, cut-off frequency, power gains and the parasitic capacitances. The results are, thus, useful for optimizing the performance and reliability of nanoscale L-DUMGAC MOSFETs for high-speed logic, switching and RF applications.

Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design

The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: V IP2 , V IP3 , IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device’s bias point for RFICs with higher efficiency and better linearity performance.

Study on the relation between structure and hot carrier effect immunity for deep sub-micron grooved gate NMOSFET’S

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region, for it can suppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energy transport model, using two-dimensional device simulator Medici, the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET’s is studied and compared with that of counterpart conventional planar device in this paper. The examined structure parameters include negative junction depth, concave corner and effective channel length. Simulation results show that grooved gate device can suppress hot carrier effect deeply even in deep sub-micron region. The studies also indicate that hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device. With the increase of concave corner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducing of effective channel length, the hot carrier effect becomes large.

The influence of geometric structure on the hot-carrier-effect immunity for deep-sub-micron grooved gate PMOSFET

Based on the hydrodynamics energy transport model, the influence of geometrical structure parameters on the hot-carrier-effect immunity in deep-sub-micron grooved gate PMOSFET's is studied. The study results are explained based on the device's interior physical mechanism. The structure parameters investigated include the effective channel length, the concave corner and the negative junction depth induced by changing the source/drain junction depth or groove depth. The research results indicate that the hot-carrier effect is depressed deeply for grooved gate PMOSFET's even in deep and super-deep-sub-micron regions, and with the increase of the concave corner and the negative junction depth, the hot-carrier-effect immunity becomes better. Those are mainly because that the structure parameters influence the distribution of the electric field in the devices, which influence the “corner effect” and the transportation of the carriers.