Negative Gate Bias Stress Research Articles

Amorphous InZnSnO Thin-Film-Transistors Performance Enhancement with Low-Energy Xenon Pulsed-Light Annealing

The electrical characteristics and stability of amorphous indium-zinc-tin oxide (IZTO) thin-film transistors (TFTs) were significantly improved in this study using low-energy Xenon pulsed-light annealing (PLA). In comparison to conventional furnace annealing (FA), PLA treatment significantly reduced the processing temperature and annealing time. Besides, the defect states are obviously reduced from 1.73×1012 cm-2 to 6.53×1011 cm-2 by PLA treatment, resulting in improved device electrical characteristics and enhanced reliability, including improved carrier mobility from 20.08 to 39.61 cm2/V∙s, threshold voltage from 0.82 to 0.24 V, subthreshold swing (S.S.) from 0.54 to 0.24 V/decade, and the ON/OFF current ratio from 2.32×107 to 7.31×108. In addition, the enhanced stability is observed under both positive gate-bias stress (PGBS) of VGS = 30 V and negative gate-bias stress (NGBS) of VGS = –30 V for a stress duration of 3000 s. The threshold voltage shift (ΔVTH) is reduced from 8.31 V to 1.65 V and from –3.93 V to –1.51 V, respectively. This is the first time low-energy PLA was conducted for IZTO TFT performance improvement.

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

High-throughput methodology for the realization of high-entropy sub-nm equivalent-oxide-thickness high-dielectric-constant Ba(Ti,Zr,Ta,Hf,Mo)O3 film-based metal-oxide-semiconductor-related devices

This paper reports the use of a high-throughput sputtering technique for the fabrication of high-entropy high-dielectric-constant (high-k) Ba(Ti,Zr,Ta,Hf,Mo)O3 film libraries on Si substrates and sub-nm equivalent-oxide-thickness (EOT) metal−oxide−semiconductor (MOS) devices and metal−oxide−semiconductor field-effect transistors (MOSFETs). The elemental variations and amorphous microstructures are characterized using high-throughput X-ray fluorescence (XRF) and X-ray diffraction, respectively. The film library was patterned into 100 MOS configurations and the films with (Ba + Ti) = 0.41−0.47 at.%, (Mo + Zr) = 0.28−0.34 at.%, and (Ta + Hf) = 0.23−0.3 at.% exhibited favorably high k (325−374) and low tan δ (0.01−0.08) values with an impressive EOT ≈ 0.8−0.94 nm. The resulting MOSFETs after the rapid thermal annealing (RTA) exhibited excellent characteristics: an on/off current ratio of 8 × 106, saturated field-effect mobility of 138.4 cm2 V−1 s−1, a threshold voltage (VT) of 0.03 V, a subthreshold swing of 0.062 V⋅dec−1, and low interfacial defects of approximately 5.6 × 1010 eV cm−2. Small ΔVT and negligible changes in the maximum drain current were observed for the MOSFETs under various positive and negative gate-bias stress conditions before and after the RTA. Our devices outperformed various reported transistors, indicating the potential of the Ba(Ti,Zr,Ta,Hf,Mo)O3 films for use in a gate-first process for advanced gate stack-related devices.

In-situ fluorine-doped ZnSnO thin film and thin-film transistor

In this paper, in-situ fluorine-doped ZnSnO (ZTO:F) thin films prepared by co-sputtering are proposed. It was found that the F had been successfully introduced into the ZTO thin films and distributed uniformly in the bulk. The corresponding top-contact bottom-gated ZTO:F thin film transistors (TFTs) were fabricated with an annealing temperature of 350 °C. The fabricated TFTs exhibit a field-effect mobility of 14.2 cm2V−1s−1, on-off ratio of over 109, and subthreshold swing (SS) as low as 87 mV/decade due to the incorporation of F. In addition, the bias stability of fabricated TFTs was also examined and the Vth shifts under negative gate bias stress are not more than ±0.1 V even without any passivation. It is expected that the In-free ZTO:F amorphous oxide semiconductor and the corresponding TFTs have potential for low-cost and environmentally safe fabrication.

Performance and stability of Al-doped HfGaO thin-film transistors deposited by vapor cooling condensation system

In this work, to study the features of Al atomic ratio in Al2O3-doped HfGaO (referred as AlHfGaO) channel layers of thin-film transistors, the HfGaO and various AlHfGaO films were deposited at approximately 80 K using a vapor cooling condensation system. The oxygen vacancy defects resided in AlHfGaO films and the defect density in the resulting thin-film transistors decreased with an increase of the Al atomic ratio. As defects reduced, threshold voltage and on/off current ratio increased, while threshold voltage offset and subthreshold swing decreased. In terms of the threshold voltage offset, measured by positive gate bias stress and negative gate bias stress methods, as the stability parameter of thin-film transistors, the stability was improved by using a higher Al atomic ratio in the AlHfGaO channel layers due to the suppression of the charge trapping effect.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene).

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 107 was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.

Abnormal Degradation Behaviors Under Negative Bias Stress in Flexible p-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors After Laser Lift-Off Process

This work investigates the abnormal phenomena that are observed in electrical characteristics under negative bias stress (NBS) in flexible p-channel low-temperature polycrystalline silicon thin-film transistors (p-channel LTPS TFTs) after TFTs being lifted off from a rigid substrate. During the lift-off process, mechanical strain accumulates in the buffer layer due to the unilateral force, thus resulting in the generation of defects in the buffer layer. Therefore, abnormal degradation behaviors in electrical characteristics of the lifted-off TFTs were observed during negative gate bias stress. A study on physical mechanisms is introduced to describe such abnormal phenomena, and it is confirmed that defects are produced in the buffer layer when the LTPS TFTs are lifted off. In addition, different device dimensions were discussed to support our proposed model. The findings in this work are supported by the discussion of electrical characteristics, trap state extraction, and COMSOL simulation.

Microwave-Irradiated Metal-Oxide Thin-Film Transistors With Recessed Gate Structure and Their Applications in Logic Circuits

The effects of a recessed gate structure on the device performance of sol-gel-based metal-oxide thin-film transistors (oxide-TFTs) consisting of aluminum oxide dielectric and indium-gallium-zinc oxide semiconducting films fabricated through effective microwave irradiation are investigated, as compared with elevated and non-patterned gate structures. Low-voltage operating oxide-TFTs with an optimized recessed gate structure exhibited improved device performance including OFF-state current of approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{11}}$ </tex-math></inline-formula> A and field-effect mobility of 3.4 cm2/V-s in the linear regime, compared with those with elevated (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{9}}$ </tex-math></inline-formula> A and 1.9 cm2/V-s) and non-patterned (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{10}}$ </tex-math></inline-formula> A and 2.8 cm2/V-s) gate structures. Furthermore, the charge transport mechanism responsible for improved device performance and operational stability against prolonged positive and negative gate bias stresses in the oxide-TFTs with the recessed gate structure is investigated through activation energy and velocity distribution that are determined from direct-current and time-domain non-quasi-static transient analyses, respectively. Finally, enhancement-load-type nMOS inverters operating at 5 V are developed for logic circuits, which exhibit a relatively high dc gain of 32.2 in the recessed gate structure, compared with that of 17.1 and 27.1 in the elevated and the non-patterned gate structures, respectively.

Suppression of Kink in the Output Characteristics of AlInN/GaN High Electron Mobility Transistors by Post-Gate Metallization Annealing

In this paper, we report the effect of post-gate metallization annealing on the performance of GaN-based High Electron Mobility Transistors (HEMTs). The performances of HEMTs annealed at 200 °C (HEMT1) and at 400 °C (HEMT2) for 5 minutes in N2 ambient are compared. While there is a kink in the output characteristics of HEMT1, there is no such kink in the output characteristics of HEMT2. The kink is attributed to impact ionization in the GaN channel. Surface and interface traps of HEMT1 increase the peak electric field at the drain side gate edge and cause impact ionization. The post-gate metallization annealing at a higher temperature reduces the surface and interface traps, which reduces the peak electric field in HEMT2 and suppresses impact ionization. This is substantiated by TCAD simulations. Threshold voltage instability on the application of negative gate bias stress was also examined for these devices. A positive shift in threshold voltage was observed in HEMT1 on the application of negative gate bias stress, whereas the corresponding shift was negative in HEMT2, indicating the presence of two different types of traps in HEMT1 and HEMT2.

Low‐Voltage, High‐Performance, Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Based on Dual‐Channel and Anodic‐Oxide

AbstractOxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic AlxOy film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic AlxOy exhibits an effective saturation mobility of 12.56 cm2 Vs−1, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec−1, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔVTH) &lt; −0.03 V under a negative gate bias stress and ΔVTH &lt; 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.

Effect of Back-Channel Surface on Reliability of Solution-Processed In0.51Ga0.15Zn0.34O Thin-Film Transistors with Thin Active Layer.

We have investigated the degradation mechanism of solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors. The threshold voltage shift (ΔVth) followed a linear function under negative gate bias stress (NBS), while it showed a stretched-exponential behavior under positive gate bias stress. The slope of ΔVth for stress time was rarely changed with variations below 0.3 mV/s. The thickness of the fabricated IGZO layer (In0.51Ga0.15Zn0.34O) was approximately 10 nm. The Debye length (LD) was larger than IGZO thickness (tIGZO) due to the fully depleted active layer under NBS. Therefore, the degradation phenomenon under NBS was related to the adsorption at back-channel surface. The back-channel surface could be affected by the gate bias under NBS, and the molecules adsorbed at the IGZO layer were positively charged and induced extra electrons by NBS. We verified that the number of positively charged adsorbates had a proportional relationship with the ΔVth based on the two-dimensional technology computer-aided design (TCAD) simulation. Furthermore, we investigated the degradation phenomenon with the ΔVth equation regarding the adsorbates, and the result confirmed that the adsorption process could cause the linear ΔVth. We experimentally confirmed the effect of back-channel surface by comparing the ΔVth between different atmospheric conditions and LD. Consequently, the reaction at the back-channel surface should be considered to develop the metal-oxide semiconductor devices.

Effect of Humidity on Properties of Aqueous-Processed Tb-Doped Indium Oxide Thin-Film Transistors

Aqueous route is readily for fabricating oxide thin-film transistors (TFTs), but the relative humidity (RH) impacts evolution of oxide thin films. Herein, the effect of RH on the electronic performance and bias stability of aqueous-processed Tb-doped indium oxide (Tb:In2O3) TFTs is investigated. The mobility is sensitive to RH. By tuning the RH for desirable thickness and density of the obtained Tb:In2O3 films, the TFTs present optimized mobility of 13.0 cm2/Vs, with high ON/OFF ratio of 108. Notably, low threshold voltage shift of −0.35 V and 0.42 V under negative and positive gate bias stress are simultaneously obtained with a fabricating RH of 40%. Moreover, dry ambience (RH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le23$ </tex-math></inline-formula> %) affords to abundant nanopores and defects, resulting in inferior performance and stability of the aqueous-processed oxide TFTs. And high humid ambience easily ruins the uniform of precursor films. This work indicates the strategy to fabricate highly stable oxide TFTs with high performance.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

Improved Stability With Atomic-Layer-Deposited Encapsulation on Atomic-Layer In2O3 Transistors by Reliability Characterization

Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> engineering by an O2 plasma treatment. After treatment, the magnitude of long-term <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.

Improvement in Short-Channel Effects of the Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel Compositions

In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \mu \text{m}$ </tex-math></inline-formula> to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula> .

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization.

In this work, temperature-dependent transient threshold voltage (VT) instability behaviors in p-GaN/AlGaN/GaN HEMTs, with both Schottky gate (SG) and Ohmic gate (OG), were investigated systematically, under negative gate bias stress, by a fast voltage sweeping method. For SG devices, a concave-shaped VT evolution gradually occurs with the increase in temperature, and the concave peak appears faster with increasing reverse bias stress, followed by a corresponding convex-shaped VT recovery process. In contrast, the concave-shaped VT evolution for OG devices that occurred at room temperature gradually disappears in the opposite shifting direction with the increasing temperature, but the corresponding convex-shaped VT recovery process is not observed, substituted, instead, with a quick and monotonic recovery process to the initial state. To explain these interesting and different phenomena, we proposed physical mechanisms of time and temperature-dependent hole trapping, releasing, and transport, in terms of the discrepancies in barrier height and space charge region, at the metal/p-GaN junction between SG and OG HEMTs.