Negative Channel Metal Oxide Semiconductor Research Articles

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large-Scale Integration (VLSI) circuit designs. Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror of voltage comparator. NMOS is used to reduce stacking leakage as well as total exchange. Domino Logic Circuit is a powerful and versatile digital programmer that gained popularity in recent years. In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control (ASVLC)-based domino circuit. The efficiency and effectiveness of the domino circuit are demonstrated through simulation results. The suggested system makes use of high-speed broad fan-gate circuits, occupies minimum space, and consumes meagre amount of power. The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V, frequency of 100 MHz, and an operating temperature of 27°C with 64 input OR gates. As per the simulation results, the suggested Domino Gate reduced the power dissipation by 17.58 percent and improved the noise immunity by 1.21 times in comparison with standard domino logic circuits.

CMOS Transistors Based First-Order Voltage-Mode All-Pass Filter with Tunable Transformation Possibility

In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18[Formula: see text][Formula: see text]m level-7 CMOS process parameters.

Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC

Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 μm BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of 62° for a load capacitance of 2 pF. Output voltage swings are ±3.71 V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162 μm × 200.82 μm. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.

High-Yield Ti3 C2 Tx MXene-MoS2 Integrated Circuits.

It is very challenging to employ solution-processed conducting films in large-area ultrathin nanoelectronics. Here, spray-coated Ti3 C2 Tx MXene films as metal contacts are successfully integrated into sub-10nm gate oxide 2D MoS2 transistor circuits. Ti3 C2 Tx films are spray coated on glass substrates followed by vacuum annealing. Compared to the as-prepared sample, vacuum annealed films exhibit a higher conductivity (≈11 000 S cm-1 ) and a lower work function (≈4.5eV). Besides, the annealed Ti3 C2 Tx film can be patterned through a standard cleanroom process without peeling off. The annealed Ti3 C2 Tx film shows a better band alignment for n-type transport in MoS2 channel with small work function mismatch of 0.06eV. The MoS2 film can be uniformly transferred on the patterned Ti3 C2 Tx surface and then readily processed through the cleanroom process. A large-area array of Ti3 C2 Tx MXene-MoS2 transistors is fabricated using different dielectric thicknesses and semiconducting channel sizes. High yield and stable performance for these transistor arrays even with an 8nm-thick dielectric layer are demonstrated. Besides, several circuits are demonstrated, including rectifiers, negative-channel metal-oxide-semiconductor (NMOS) inverters, and voltage-shift NMOS inverters. Overall, this work indicates the tremendous potential for solution-processed Ti3 C2 Tx MXene films in large-area 2D nanoelectronics.

MPPT Circuit Using Time Exponential Rate Perturbation and Observation for Enhanced Tracking Efficiency for a Wide Resistance Range of Thermoelectric Generator

The thermoelectric generator (TEG) stands out among many energy harvesters due to its simple structure, small size, rich thermal energy, and the absence of pollution and noise. However, previous studies have rarely probed into the influence of TEG internal resistances on extracting maximum power from TEGs, and the tracking of efficiency is limited. By analyzing the relationship between the tracking efficiency and the TEG internal resistances, a time exponential rate perturbation and observation (P&O) technology is proposed to achieve maximum power point tracking (MPPT) for a wide resistance range of the TEG. Using the time exponential rate P&O, the MPPT circuit observed the power change by comparing the positive-channel metal-oxide semiconductor (PMOS) on-time and perturbs the power by adjusting the negative-channel metal-oxide semiconductor (NMOS) on-time exponentially. The MPPT circuit was implemented in a 110 nm complementary metal-oxide semiconductor (CMOS) process. The tracking efficiency maintained a high level from 98.9 to 99.5%. The applicable range of the TEG resistance was from 1 to 12 Ω, which reflects an enhancement of at least 2.2 times.

A Frequency and Radiation Pattern Combo-Reconfigurable Novel Antenna for 5G Applications and Beyond

This paper presents a novel combo-reconfigurable architecture for the frequency and radiation patterning of a novel antenna system for future fifth-generation (5G) millimeter-wave mobile communication. The tuning system independently controls the frequency and radiation pattern shifts, without letting them affect each other. The proposed antenna consists of two patches, radiating at 28 GHz and 38 GHz. A negative-channel metal–oxide–semiconductor (NMOS) transistor was used as a switch for ON/OFF states. Frequency reconfiguration was controlled by switches SD1 and SD2, while pattern reconfigurability was achieved by SD3–SD18. The desired resonant frequencies of 28 GHz and 38 GHz were achieved by varying patch dimensions through the ON and OFF states of the SD1 and SD2 switches. Similarly, parasitic stubs on the ground are used to control surface currents, which results in pattern reconfiguration. The results were analyzed for 18 different combinations of the switch states. Adding/removing parasitic stubs and switches changed the beam steering angle (by 45° shift) from 0° to 180°, which modified the stub dimensions and changed the beam-width of the main lobe.

A 60 mV Input Voltage, Process Tolerant Start-Up System for Thermoelectric Energy Harvesting

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of $4.5~\mu \text{W}$ from a 60 mV supply. This system has been implemented in a standard $0.18~\mu \text{m}$ CMOS technology, uses neither zero-threshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2.

HSPICE model and circuit simulation for a single-event effect caused by ions at different incident positions

A 3D model of the negative-channel metal-oxide semiconductor (NMOS) structure in a 65-nm complementary metal-oxide semiconductor (CMOS) inverter was built based on technology computer-aided design (TCAD) three-dimensional (3D) device simulation software. The single-event effect caused by a heavy ion at different incident positions was simulated and analyzed using the TCAD–HSPICE mixed-mode simulation. Then, an analytical model was established to describe the relationship between the incident position of the ion and the charge collected by the NMOS drain. Finally, an HSPICE simulation approach based on this model was developed and verified by simulations.

Atomic‐Layer‐Deposited SnO2 as Gate Electrode for Indium‐Free Transparent Electronics

Atomic‐layer‐deposited SnO2 is used as a gate electrode to replace indium tin oxide (ITO) in thin‐film transistors and circuits for the first time. The SnO2 films deposited at 200 °C show low electrical resistivity of ≈3.1 × 10−3 Ω cm with ≈93% transparency in most of the visible range of the electromagnetic spectrum. Thin‐film transistors fabricated with SnO2 gates show excellent transistor properties including saturation mobility of 15.3 cm2 V−1 s−1, a low subthreshold swing of ≈130 mV dec−1, a high on/off ratio of ≈109, and an excellent electrical stability under constant‐voltage stressing conditions to the gate terminal. Moreover, the SnO2‐gated thin‐film transistors show excellent electrical characteristics when used in electronic circuits such as negative channel metal oxide semiconductor (NMOS) inverters and ring oscillators. The NMOS inverters exhibit a low propagation stage delay of ≈150 ns with high DC voltage gain of ≈382. A high oscillation frequency of ≈303 kHz is obtained from the output sinusoidal signal of the 11‐stage NMOS inverter‐based ring oscillators. These results show that SnO2 can effectively replace ITO in transparent electronics and sensor applications.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030) and the Advanced Research Project of National University of Defense Technology, China (Grant No. 0100066314001).

In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon–germanium (SiGe) BiCMOS 130nm technology and achieves a better than 21.96dBc SFDR across the Nyquist band for a sampling rate of 500MS/s with a core size of 0.1mm2 and dissipates just 4mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

High performance of low voltage controlled ring oscillator with reverse body bias technology

In complementary metal oxide semiconductor (CMOS) nanoscale technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27°C with supply voltage V dd = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator (VCO) in term of minimum leakage power (1.23 nW) and maximum oscillation frequency (4.76 GHz) with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor (PMOS and NMOS) reverse substrate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

A compact model of substrate resistance for deep sub-micron gate grounded NMOS electrostatic discharge protection device

The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors

This paper presents the fabrication of a negative-channel metal–oxide–semiconductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic.

Nanobeam Diffraction: Technique Evaluation and Strain Measurement on Complementary Metal Oxide Semiconductor Devices

Nanobeam electron diffraction (NBD) is a transmission electron microscopy (TEM) technique that allows determining strain in crystalline materials with a high spatial resolution. In particular, it can be used to measure local strain in the Si channel of metal oxide semiconductor (MOS) devices. In this work, the NBD technique is evaluated with the purpose to optimize its different parameters, such as the thickness of the TEM specimen and the width of the energy filtering window, and to further estimate its precision. Strain is then measured in positive-channel MOS (PMOS) and negative-channel MOS (NMOS) devices with different gate length and Ge or C concentration in the source/drain respectively. The results are compared with optical and electrical characterization, finite-element simulations and to other strain measuring TEM-based techniques.

Total dose radiation effects on SOI NMOS transistors with different layouts

Partially-depleted Silicon-On-Insulator Negative Channel Metal Oxide Semiconductor (SOI NMOS) transistors with different layouts are fabricated on radiation hard Separation by IMplanted OXygen (SIMOX) substrate and tested using 10 keV X-ray radiation sources. The radiation performance is characterized by transistor threshold voltage shift and transistor leakage currents as a function of the total dose up to 2.0×106 rad(Si). The results show that the total dose radiation effects on NMOS devices are very sensitive to their layout structures.

A Wide Dynamic Range Photogate-Type Active Pixel Sensor Using a Self-Regulation Principle

A wide dynamic range photogate-type active pixel image sensor based on a self-regulation principle is reported. A 5 ×5 element prototype sensor was fabricated using a 5 µm single-poly, single-metal negative channel metal oxide semiconductor (NMOS) silicon integrated circuit technology. The key techniques are based on the feedback of a floating diffusion (FD) potential to the photogate applied voltage and on the control of the sub-threshold characteristic of the photogate using an ion implantation process. The proposed sensor makes it possible to automatically adjust the sensitivity of each pixel using only three transistors. The conversion of the irradiated light to the output voltage is linear under low-light conditions, while it is nonlinear under bright light. The photo-electric conversion characteristics are similar to those of a linear-logarithmic image sensor. The dynamic range can be expanded without the need for an additional capacitor, an analog-to-digital (A/D) converter or any complex circuitry. Compared with a conventional photogate-type image sensor that was fabricated on the same chip, the dynamic range was expanded by 28 dB.

Dual-metal-gate-integration complementary metal oxide semiconductor process scheme using Ru positive-channel metal oxide semiconductor and TaC negative-channel metal oxide semiconductor gate electrodes

This article presents the development of a wet removal process on the integration of complementary metal oxide semiconductor (CMOS) dual metals with Ru for positive-channel metal oxide semiconductor and TaC for negative-channel metal oxide semiconductor on high-k HfO2 gate dielectric. The integration scheme focused on the wet etching capability for the first metal and the selectivity control on the high-k dielectrics under the metal gate. Using the developed chemical, ceric ammonium nitrate and nitric acid mixture used for Ru metal removal and HfO2 treated with Ar∕O2 plasma by selective diluted hydrofluoric wet etching, a CMOS dual-metal-gate structure was achieved with satisfactory device fabrication.

Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate Electrode

Constant voltage stress induced Vth shift and its detrapping characteristics under the negative gate bias has been extensively investigated with HF-silicate dielectrics with poly and TiN gate electrode. The threshold voltage shift in negative-channel metal-oxide semiconductor (NMOS) transistors under the positive gate bias stress is found to be associated mostly with the reversible electron trapping. A proper negative bias can be used to de-trap the electrons accumulated during the positive stress. However, an aggressive de-trapping can cause an additional Vth instability due to the excessive de-trapping of existing charge or additional hole trapping at the interface with poly gate. TiN metal gate is found to be more stable with de-trapping negative gate bias. To de-trap the electrons accumulated in the dielectric during the positive constant voltage stress (CVS), the negative bias and its duration should be chosen very carefully to avoid the additional charging associated with the hole trapping.