Negative Bias Temperature Instability Recovery Research Articles

7‐1: Distinguished Paper: Alleviation of Abnormal NBTI Phenomenon in LTPS TFTs on Polyimide Substrate for Flexible AMOLED

This letter investigates the negative‐bias temperature instability (NBTI) behavior of p‐channel low‐temperature polycrystalline silicon thin‐film transistors (LTPS TFTs) on plastic substrate. The measurements reveal that the threshold‐voltage positive shift is highly correlated to the passivation of grain‐boundary trap states. By applying the established phenomenon such as NBTI recovery and H diffusion from PI substrate, a new model is introduced to explain mechanism and verified by the experiment. With the thick buffer & bottom metal layer or newly processed PI substrate, we succeeded in adjusting the NBTI behavior of LTPS TFTs on plastic substrate.

Alleviation of abnormal NBTI phenomenon in LTPS TFTs on polyimide substrate for flexible AMOLED

AbstractThis letter investigates the negative‐bias temperature instability (NBTI) behavior of p‐channel low‐temperature polycrystalline silicon thin‐film transistors (LTPS TFTs) on plastic substrate. The measurements reveal that the threshold‐voltage positive shift is highly correlated to the passivation of grain boundary trap states. By applying the established phenomenon such as NBTI recovery and H diffusion from PI substrate, a new model is introduced to explain the mechanism and verified by the experiment. With the thick buffer and bottom metal layer or newly processed PI substrate, we succeeded in adjusting the NBTI behavior of LTPS TFTs on plastic substrate.

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency.

Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery

As the Internet of Things continues to spread, devices within it are given more personal information which must be protected. To provide this protection, a device known as a physical unclonable function (PUF) has been devised which takes advantage of natural variations in silicon to create a unique fingerprint which can be used for secret key generation and authentication. This fingerprint is often based upon settlement of a race condition in competing circuits which is decided by process variations and noise. In this paper, we focus on the SRAM PUF, whose fingerprint is determined by the tendency of each cell to contain a 0 or 1 after it powers on. These cells are susceptible to negative-bias temperature instability (NBTI) while storing data, which pushes their power-on tendencies away from the data they contain. We present a method by which the success rate of an SRAM to produce a correct fingerprint can be reduced to 0% in only one day using NBTI activated and accelerated by elevated voltage and temperature, followed by another method in which it can be restored to nearly 100% in less than two days using active, accelerated NBTI recovery with negative voltage and elevated temperature.

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions

Threshold voltage shift ( $\Delta {\text V}_{\text T}$ ) due to negative-bias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps ( $\Delta {\text V}_{\text {IT}}$ ), hole trapping in preexisting ( $\Delta {\text V}_{\text {HT}}$ ), and generation of new ( $\Delta {\text V}_{\text {OT}}$ ) bulk insulator traps is used to quantify measured data. The model can explain dc stress and recovery data over an extended temperature range (−40 °C to 150 °C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of $\Delta {\text V}_{\text {IT}}$ , $\Delta {\text V}_{\text {HT}}$ , and $\Delta {\text V}_{\text {OT}}$ , and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods.

Mixture of negative bias temperature instability and hot-carrier driven threshold voltage degradation of 130 nm technology p-channel transistors

We present measurement results in form of threshold voltage drift plots, recovery traces and continuous capture emission time maps (CET maps) including Negative Bias Temperature Instability (NBTI) and Hot-Carrier driven Degradation (HCD). The measurements were performed on a 130nm MOS transistor technology which is used for automotive and analog applications and has a nominal voltage of 1.5V. Devices of l=100nm, w=10μm have been stressed using a 2-dimensional parameter space of gate and drain voltage combinations at elevated temperature (125°C). The chosen stress conditions include the homogeneous (Vds=0) and inhomogeneous (Vds≪Vnom) NBTI case, the pure HCD (Vgs<Vnom) case as well as the mixture of NBTI and HCD. The results clearly show that for increasing Vds>Vnom NBTI recovery becomes less severe and mainly the permanent degradation due to HCD endures after the end of stress. Furthermore there is a drift minimum of NBTI observable for a specific Vds. Using CET maps it is quite evident that for high stress times the probability density of emission becomes very small whereas for shorter stress times there is a recoverable component notable.

Effect of fluorine implantation on recovery characteristics of p-channel MOSFET after negative bias temperature instability stress

In this paper, the effect of fluorine implantation on the recovery characteristics of p-channel MOSFETs (PMOSFETs) after negative bias temperature instability (NBTI) stress was investigated. PMOSFETs using fluorine ion implantation (F-I/I) performed better than those without F-I/I after NBTI stress; it is thought that F-I/I can suppress the generation of permanent damage during NBTI stress. The relationship of ΔVth and ΔSS during NBTI stress and recovery showed how much permanent damage occurred. In addition, we confirmed with a 1/f noise measurement that the device with F-I/I was immune to NBTI stress in spite of a pre-existing bulk trap caused by implantation damage. Moreover, the device with F-I/I had greater activation energy than the device without F-I/I. As indicated by the results, fluorine implantation can decrease the generation of permanent damage under NBTI stress because of the stable Si–F bond.

Statistical analysis of relationship between negative-bias temperature instability and random telegraph noise in small p-channel metal–oxide–semiconductor field-effect transistors

It is demonstrated from a statistical perspective that the generation of random telegraph noise (RTN) changes before and after the application of negative-bias temperature instability (NBTI) stress. The NBTI stress generates a large number of permanent interface traps and, at the same time, a large number of RTN traps causing temporary RTN and one-time RTN. The interface trap and the RTN trap show different features in the recovery process. That is, a re-passivation of interface states is the minor cause of the recovery after the NBTI stress, and in contrast, rapid disappearance of the temporary RTN and the one-time RTN is the main cause of the recovery. The RTN traps are less likely to become permanent. This two-type trap, namely, the interface trap and RTN trap, model simply explains NBTI degradation and recovery in scaled p-channel metal–oxide–semiconductor field-effect transistors.

On the Distribution of NBTI Time Constants on a Long, Temperature-Accelerated Time Scale

Recent investigations on individual defects contributing to negative bias temperature instability (NBTI) showed that the emission and capture time constants are thermally activated via an Arrhenius law. We apply this finding to conventional micrometer-sized devices where NBTI is the response of up to millions of defects. We rapidly switch the device temperature using an on-chip heating structure in order to accelerate NBTI stress and recovery and acquire experimental data on an up to 18 decades long time scale. On this extended time scale, we find that the distribution of NBTI defect time constants is log-normal with large mean and variance which follows directly from a normal distribution of energy barriers in Arrhenius law. As such, our work clearly identifies the role of temperature for NBTI and suggests a method for accurate life-time estimations.

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

We propose a multicore large-scale integration (LSI) lifetime extension method, which is based on negative bias temperature instability (NBTI) recovery-based self-healing and circuit parallelization. NBTI recovery is characterized by the recently proposed NBTI sensor with 400 ns measurement delay that measures the off-leak current of p-channel metal–oxide–semiconductor (PMOS) transistors. The circuit is fabricated in a commercial 65 nm complementary MOS (CMOS) technology. It is found that the recoverable component of the LSI performance characterized by the off-leak current remains almost constant after repeatedly adding NBTI stress. The NBTI stress corresponds to circuit operation for several years at room temperature and a nominal operating voltage. It is also found that the amount of NBTI recovery can be tuned by the relaxation time in a real application, and it follows log t from 400 ns to 3000 s. It is shown that for multicore LSI, by recovering one of the n + 1 cores, the n-core LSI system does not stop and the lifetime can be extended by NBTI recovery. For the first time, transforming silicon area into LSI reliability is shown to be a promising and realistic concept for the ever-shrinking CMOS technology.

A 65 nm Complementary Metal–Oxide–Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit

We propose a negative bias temperature instability (NBTI) recovery sensor with a 400 ns measurement delay. The measurement delay is about 30 ms when the leakage current of a small single transistor is measured by the conventional method. This sensor contains many unit cells. One unit cell includes 10 p-channel metal–oxide–semiconductor (PMOS) Device-under-tests (DUTs) and two assist n-channel metal–oxide–semiconductor (NMOS) devices. Parallelizing many unit cells can amplify the leakage current and the assist circuit can reduce the rush current to the ammeter, which keeps the measurement range of the ammeter constant during measurement. A short measurement delay is achieved by these two factors. It is confirmed that from 50 to 125 °C, NBTI recovery follows log t from 400 ns to 3000 s. By stressing and recovering thousands of PMOS transistors at the same time, we can observe that the time constants of positively charged defects, which are related to NBTI, are log-uniformly distributed in the PMOS devices. Also, this circuit has the highest fidelity to NBTI recovery measurement because off-leak current is used for NBTI recovery characterization and stress is not added during measurement.

Charge Gain, NBTI, and Random Telegraph Noise in EEPROM Flash Memory Devices

Different charge-gain (CG) processes are reported in EEPROM nonvolatile Flash memory devices. The process originally characterized in nitride-trapping devices is reexamined. Its mechanism is reinterpreted in terms of the recovery of negative-bias temperature instability (NBTI). We show that this CG process is controlled by nonequilibrium random-telegraph-noise-like mechanism, similar to NBTI recovery in MOS devices.

Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices

This letter identifies and investigates the effect of grain orientation (GO) on negative-bias temperature instability (NBTI) characteristics of emerging metal-gate devices. A modified reaction-diffusion model is presented for estimating the effect of GO on NBTI. It is shown that neglecting the GO effect leads to substantial underestimation of the impact of the gate-oxide electric field (EOX) on the threshold voltage degradation (ΔVTH). Moreover, GO results in significant fluctuation in EOX and, hence, fluctuation in NBTI for ultrascaled CMOS devices. In addition, in FinFETs, stand-alone GO-induced gate-oxide electric field not only results in ΔVTH fluctuation but also decelerates the recovery process.

Forward-Body-Bias-Enhanced Negative Bias Temperature Instability Recovery of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Experimental investigation on the negative bias temperature instability (NBTI) recovery of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with forward body bias (FBB) was conducted. Our results show that not only the positive gate bias but also the FBB will enhance the recovery of NBTI for pMOSFETs. A forward-body-bias-enhanced NBTI recovery mechanism was proposed with evidence of the NBTI recovery with FBB dependence and corresponding electron/hole density simulation results. Furthermore, the dynamic NBTI degradation was compared with and without FBB. The enhancement of NBTI recovery by FBB gives a comparable lifetime of zero body bias, which indicates that the forward body biasing technique can improve the drive capability without deteriorating NBTI performance.

A Common Framework of NBTI Generation and Recovery in Plasma-Nitrided SiON p-MOSFETs

Generation and recovery of degradation during and after negative bias temperature instability (NBTI) stress are studied in a wide variety of plasma-nitrided (PN) silicon oxynitride (SiON) p-MOSFETs. An ultrafast on-the-fly linear drain current (IDLIN) technique, which is capable of measuring the shift in threshold voltage from very short (approximately in microseconds) to long (approximately in hours) stress/recovery time, is used. The mechanics of NBTI generation and recovery are shown to be strongly correlated and can be consistently explained using the framework of an uncorrelated sum of a fast and weakly temperature (T)-dependent trapped-hole (?V h) component and a relatively slow and strongly T-activated interface trap (?V IT) component. The SiON process dependences are attributed to the difference in the relative contributions of ?V h and ?V IT to the overall degradation (?V T), as dictated by the nitrogen (N) content and thickness of the gate insulator.

A New NBTI Model Based on Hole Trapping and Structural Relaxation in MOS Dielectrics

Negative bias temperature instability (NBTI) is one of the major reliability concerns for analog and digital MOS devices. NBTI understanding and modeling is receiving a growing interest for failure prediction, depending on the temperature and duty cycle of dynamic-stress conditions. In this framework, we present a new NBTI model based on hole trapping and thermally activated relaxation. The model unifies previous concepts of hole tunneling/trapping and structural relaxation initiated by hole trapping. Simulation results can account for the time and temperature dependence of NBTI stress, NBTI recovery, and the dependence on thickness and nitridation technology of the gate dielectric. The numerical model may be used for physics-based reliability predictions of NBTI effects as a function of time, temperature, and stress regime.

Effect of variable body bias technique on pMOSFET NBTI recovery

A study on the negative bias temperature instability (NBTI) recovery of a pMOSFET under variable body bias (VBB) is presented. The forward body bias enhanced NBTI recovery mechanism is proposed with evidence on the VBB dependency. Further, the influence of surface potential and the gate oxide electric field on the recovery indicated that the relaxation of the positive charge and interface trap played a different role in the NBTI recovery stage. It is shown that the forward VBB technique can achieve improvement in terms of drive capability and NBTI lifetime.

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.

Negative bias temperature instability (NBTI) recovery with bake

Negative bias temperature instability (NBTI) is a major degradation mechanism of PMOSFET devices. When the p-channel field effect transistor (PFET) gate is biased negatively with respect to the channel, as in a CMOS inverter, at an elevated temperature the threshold voltage ( V t) decreases (absolute value increases for application temperatures) and the drive current ( I on) decreases. This degrades the device performance and may lead to circuit failure. NBTI has strong dependence on temperature, gate voltage, time, and gate oxide thickness. It also depends on device area and/or geometry. NBTI models used in industry are empirical. I have observed, on different (bulk and SOI) technologies, during the last several years that NBTI recovers with bake. The recovery amount and rate depend on the bake temperature. Full recovery is achieved at temperatures above 325 °C. After full recovery, the device behaves like new. Part of the NBTI recovery can be explained by piezo- and pyro-electric effect induced by the compressive nitride liner over the PFET.