Near-threshold Voltage Research Articles

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows ${\sim}$ 75% core frequency improvement at 0.84 V.

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.

A Survey of Architectural Techniques for Near-Threshold Computing

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. Low-voltage computing, specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate, and performance loss. This article surveys several recent techniques that aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlight their similarities and differences. It is hoped that this article will provide insights into state-of-the-art NTC techniques to researchers and system designers and inspire further research in this field.

A comparative study on performance and reliability of 32-bit binary adders

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Although near-threshold ( $V_{\mathrm {\mathbf {th}}}$ ) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near- $V_{\mathrm {\mathbf {th}}}$ 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub- $V_{\mathrm {\mathbf {th}}}$ leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

This paper presents a power and area efficient SAR ADC for multi-channel near threshold- voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive- array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi- channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively. Index Terms—Multi channel, Near threshold-voltage (NTV), Analog-to-digital converter (ADC), Digital-to- analog converter (DAC), Successive approximation register (SAR), Split dual-capacitive-array (S-DCA)

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Near-threshold operation enables high energy efficiency, but requires proper design techniques to deal with performance loss and increased sensitivity to process variations. In this paper, we address both issues with two synergistic approaches. First, we introduce a novel body-biasing technique to mitigate the performance loss at near-threshold voltages while not requiring any additional circuitry for the body-bias control, thereby minimizing the design effort and simplifying the systems-on-chip integration. Second, we introduce a novel statistical design methodology to efficiently and accurately evaluate the design guardband strictly needed in the worst case, thereby keeping the area cost of variations at its very minimum. A 65-nm advanced encryption standard testchip demonstrates $1.65\times $ throughput improvement over a baseline design without body biasing, and enables reliable operation over a wide voltage range (0.5–1.2 V) as opposed to traditional body-biasing schemes. In addition, our testchip achieves $1.63\times $ area efficiency improvement compared with a design based on corner analysis. Accordingly, the proposed techniques are well suited for the design of near-threshold specialized hardware with improved performance, reduced silicon area, and design effort.

Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing

Near-threshold voltage computing can significantly improve energy efficiency; however, both operating speed and resilience to parametric variation reduce as the operating voltage reaches the threshold voltage. To prevent degradation in throughput performance, more cores should contribute to computation. The corresponding expansion in the chip area, however, is likely to further exacerbate the already intensified vulnerability to variation. Variation itself results in slower cores and ample speed differences among the cores. Worse, variation-induced slowdown might prevent operation at the designated clock speed, leading to timing errors. In this article, the authors exploit the intrinsic error tolerance of emerging Recognition, Mining, and Synthesis applications to mitigate variation. RMS applications can tolerate errors emanating from data-intensive program phases as opposed to control. Accordingly, the authors reserve reliable cores for control, and they execute error-tolerant data-intensive phases on error-prone cores. They also provide a design space exploration for decoupled control and data processing to mitigate variation at near-threshold voltages.

Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage ( $V_{{\rm {th}}})$ region, where the supply voltage ( $V_{{\rm {DD}}})$ is slightly higher than $V_{{\rm {th}}}$ . When $V_{{\rm {DD}}}$ is scaled down to near $V_{{\rm {th}}}$ , the drain current becomes greatly sensitive to $V_{{\rm {DD}}}$ or $V_{{\rm {th}}}$ ; furthermore, the energy exhibits the same sensitivity as that in the super- $V_{{\rm {th}}}$ region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near- $V_{{\rm {th}}}$ region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super- $V_{{\rm {th}}}$ and near- $V_{{\rm {th}}}$ regions, which verifies that the proposed FOM is appropriate in the near- $V_{{\rm {th}}}$ region, whereas the EDP is not.

Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

A near-threshold voltage ( $V_{{\rm {th}}}$ ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super- $V_{{\rm {th}}}$ operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near- $V_{{\rm {th}}}$ region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near- $V_{{\rm {th}}}$ region. This paper proposes a read buffer with adjusted the number of fins or $V_{{\rm {th}}}$ to resolve the problems in the near- $V_{{\rm {th}}}$ region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near- $V_{{\rm {th}}}$ region.

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.

An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting

This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 μm CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near- VTH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 μA and 50 μA, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting.

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

Near-threshold-voltage (NTV) circuit is to set the operating voltage near the threshold voltage of CMOS transistors to pursue the maximum energy efficiency. However, the characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. In this paper, we proposed a new dynamic-static hybrid near threshold voltage adder design. The proposed keeper design can suppress the leakage current and avoid signal contention in the dynamic CMOS circuit, which lets the dynamic CMOS logic family can be adapted to NTV environment with excellent speed characteristics and higher energy efficiency. The proposed low leakage dynamic-static hybrid NTV 32-bits adder design can achieve the maximum energy efficiency with 161.7% enhancement as compared to the mirror adder under NTV with 0.3 V.

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization

Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Online Monitoring Systems for Performance Fault Detection

To achieve the exaFLOPS performance within a contained power budget, next generation supercomputers will feature hundreds of millions of components operating at low- and near-threshold voltage. As the probability that at least one of these components fails during the execution of an application approaches certainty, it seems unrealistic to expect that any run of a scientific application will not experience some performance faults. We believe that there is need of a new generation of light-weight performance and debugging tools that can be used online even during production runs of parallel applications and that can identify performance anomalies during the application execution. In this work we propose the design and implementation of a monitoring system that continuously inspects the evolution of running applications and the health of the system. To achieve minimum runtime overhead while maintaining the desired level of flexibility, we propose a decoupled approach in which accurate monitoring is performed at kernel-level while performance anomaly disambiguation and corrective actions are performed at user-level. We evaluate our monitoring system on a 128-core AMD Interlagos system: First, we show that the runtime overhead of the monitoring system is negligible (0-2%). Then we show how our system can be used to precisely identify performance faults in three different scenarios: OS noise, application co-scheduling and dynamic power capping.

NUCA-L1

Research has shown that operating in the near-threshold region is expected to provide up to 10× energy efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed due to process variations. Because SRAM margins can easily be violated at near-threshold voltages, their bit-cell failure rates are expected to rise steeply. Multicore processors rely on fast private L1 caches to exploit data locality and achieve high performance. In the presence of high bit-cell fault rates, traditionally an L1 cache either sacrifices capacity or incurs additional latency to correct the faults. We observe that L1 cache sensitivity to hit latency offers a design trade-off between capacity and latency. When fault rate is high at extreme Vccmin, it is beneficial to recover L1 cache capacity, even if it comes at the cost of additional latency. However, at low fault rates, the additional constant latency to recover cache capacity degrades performance. With this trade-off in mind, we propose a Non-Uniform Cache Access L1 architecture (NUCA-L1) that avoids additional latency on accesses to fault-free cache lines. To mitigate the capacity bottleneck, it deploys a correction mechanism to recover capacity at the cost of additional latency. Using extensive simulations of a 64-core multicore, we demonstrate that at various bit-cell fault rates, our proposed private NUCA-L1 cache architecture performs better than state-of-the-art schemes, along with a significant reduction in energy consumption.

Near-Threshold CNTFET SRAM Cell Design With Word-Line Boosting and Removed Metallic CNT Tolerance

In this study, we report an in-depth study of power supply reduction toward near threshold for an eight-transistor carbon nanotube (CNT) field-effect transistors SRAM cell. Near-threshold voltage has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with nonsemiconductor CNTs. Monte Carlo simulations at Vdd (power supply voltage) of 0.4 V have shown that 97.24% of the cells are functional after removing the metallic CNTs. The power saving is over 5× and the average delay is increased by 3.5× as compared to a typical Vdd of 0.9 V. To further improve yield and performance, a word-line boosting technique is explored. Read and write word lines are boosted with additional 100 mV; this in turn effectively eliminates all the write failures at the 0.4 V level and reduces read and write delays. Comparing boosted and nonboosted cells with Vdd = 0.4 V, the boosted cell has write and read delays that are faster by 3.8× and 1.7×, respectively. This cell's energy increases by less than 4% per-access in the worst case. The cell with Vdd of 0.4 V with boosted word-lines achieves the lowest energy-delay product of all the cases considered in this study, which is 52.3% and 56.9% lower than that of a boosted and nonboosted cell with Vdd of 0.9 V, respectively.

Ensuring cache reliability and energy scaling at near-threshold voltage with Macho

Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a number of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages. These schemes rely on the fault maps to identify faulty words, inevitably increasing the chip area. Besides, the relationship between word sizes and the cache failure rates is not well studied in these works. In this paper, we analyze the word substitution schemes by employing Fault Tree Model and Collision Graph Model. A novel cache architecture (Macho) is then proposed based on this model. Macho is dynamically reconfigurable and is locally optimized (tailored to local fault density) using two algorithms: 1) a graph coloring algorithm for moderate fault densities and 2) a bipartite matching algorithm to support high fault densities. An adaptive matching algorithm enables on-demand reconfiguration of Macho to concentrate available resources on cache working sets. As a result, voltage scaling down to 400 mV is possible, tolerating bit failure rates reaching 1 percent (one failure in every 100 cells). This near-threshold voltage (NTV) operation achieves 44 percent energy reduction in our simulated system (CPU $+$ DRAM models) with a 1 MB L2 cache.

Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

Implications of the Power Wall: Dim Cores and Reconfigurable Logic

Near-threshold operation can increase the number of simultaneously active cores at the expense of much lower operating frequency ("dim silicon"), but dim cores suffer from diminishing returns as the number of cores increases. At this point, hardware accelerators become more efficient alternatives. To explore such a broad design space, the authors present an analytical model to quantify the performance limits of many-core, heterogeneous systems operating at near-threshold voltage. The model augments Amdahl's law with detailed scaling of frequency and power, calibrated by circuit-level simulations using a modified Predictive Technology Model (PTM), and factors in the effects of process variations. Results show that dim cores do indeed boost throughput, even in the presence of process variations, but significant benefits are achieved only in applications with high parallelism or novel architectures to mitigate variation. Reconfigurable logic that supports a variety of accelerators is more beneficial than "dim cores" or dedicated, fixed-logic accelerators, unless the kernel targeted by fixed logic has overwhelming coverage across applications, or the speedup of the dedicated accelerator over the reconfigurable equivalent is significant.