Near-threshold Voltage Regime Research Articles

Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications

In modern integrated circuits (ICs), the near threshold voltage (NTV) regime has gained significant attention due to its potential for enabling energy-efficient and high-performance designs. Voltage level shifters (VLS) play a crucial role in facilitating signal transmission between different voltage domains, ensuring compatibility and reliable operation of ICs. However, the unique challenges posed by near threshold voltage operation necessitate a careful analysis and design of voltage level shifters to mitigate the impact of process variations, supply voltage fluctuations, and other performance limitations. This paper presents, a novel energy efficient voltage level shifter design for NTV regime. We validated the proposed VLS in an industrial 65 nm CMOS technology and ASAP7 7 nm Fin-Fet technology. The post layout parasitic extracted simulations highlight that the proposed VLS, an average improvement of ∼50 %, 37 % and 67 % in propagation delay, power dissipation and layout area, respectively, is obtained over the recently reported VLS design at a VDD = 0.4 V in 65 nm CMOS technology. At ASAP7 7 nm Fin-Fet technology, the proposed design shows an average improvement of ∼52 % and 29 % in propagation delay and power dissipation, respectively over the recently reported VLS design at VDD = 0.3 V. The proposed VLS design offers a compelling solution for achieving high-performance, energy-efficient designs in low-power applications.

Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications

With growing interest in near-threshold voltage regime (NTV) to make energy-efficient circuits, their operation has become less reliable and prone to errors. A soft error is one of the significant reliability concerns in Static random access memories (SRAM) cells, and due to technology scaling, the sensitivity of these SRAM cells to soft errors has increased. The SRAM memories are more susceptible to the radiation effects, mainly Single Event Upsets (SEU). This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. We implement the novel memory cell in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg.

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, in this article, we propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime. Precisely, 1) we formulate the problem of finding an efficient configuration of monitoring circuits into an instance of optimal experiment design problem and 2) propose a new timing prediction flow, consisting of statistical estimation of FEOL and BEOL process variations and a neural network-based timing inference model. For accurate control of timing margin and overcoming simulation-silicon discrepancies, 3) we introduce uncertainty learning in the prediction model construction and calibrate it through transfer learning. Furthermore, 4) we avoid time-consuming SPICE simulations in our methodology by employing efficient but accurate surrogate models. Through simulations using a 28-nm industry PDK and DK characterized at 0.6-V operation, it is shown that our methodology is highly effective, reducing the average prediction pessimism of maximum delay by 77.9% over conventional signoff results while respecting target prediction yield. Besides, for test chips fabricated using a 10-nm process, we demonstrated that our holistic approach from design to postsilicon phase in conjunction with adaptive voltage scaling reduces dynamic power consumption by 28.2%–28.8% on average, in comparison with typical supply voltage operation.

A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where nonlinearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, Ieff model. The Ieff is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and Ieff of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topologybased and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime.

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

Variation-Aware Prediction of Circuit Performance in Near-Threshold Regime Using Supply-Independent Transition Threshold Points

Due to the highly variation-prone nature of the near-threshold voltage (NTV) circuits, it is critical to have design and performance models that consider process, voltage, and temperature (PVT) variations. However, in the NTV regime, the existing timing models are based on arbitrarily chosen ${V}_{\text {DD}}$ -dependent threshold points for effective current calculation that results in unreliability. In this article, an effective current delay model for an inverter operating in NTV regime is presented using supply-independent threshold points. The model is developed considering the input–output coupling capacitance and by relating the input and output currents of an inverter stage. This approach is physics-/topology-based and is valid for different technologies. This has been verified against HSPICE simulations and Synopsys Sentaurus 3-D technology computer-aided design (TCAD) simulations for STM 65-nm MOSFETs and 16-nm fin-shaped field-effect transistors (FinFETs), respectively, at different supply voltages, considering variation in threshold voltage and at different operating temperatures. The model predicts the transition delay values with an average (maximum) error of 3% (6%) and 4% (6%) for MOSFET and FinFET, respectively. Furthermore, the model is employed for digital buffer chain and single-ended ring oscillators (SEROs) for a wide range of supply voltages. Finally, we show an application of the model to calculate the change in the oscillation frequency of SERO with PVT variations and compare the same with the time-consuming Monte Carlo simulations.

Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts.

A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime

There has been a growing interest in implementing complex machine learning algorithms such as convolutional neural networks (CNNs) on lower power embedded platforms to enable on-device learning and inference. Many of these platforms are to be deployed as low power sensor nodes with low to medium throughput requirement. Near threshold voltage (NTV) designs are well-suited for these applications but suffer from a significant increase in variations. In this paper, we propose a variation-tolerant architecture for CNNs capable of operating in NTV regime for energy efficiency. A statistical error compensation (SEC) technique referred to as rank decomposed SEC (RD-SEC) is proposed. The key idea is to exploit inherent redundancy within matrix-vector multiplication (or dot product ensemble), a power-hungry operation in CNNs, to derive low-cost estimators for error detection and compensation. When evaluated in CNNs for both the MNIST and CIFAR-10 datasets, simulation results in 45 nm CMOS show that RD-SEC enables robust CNNs operating in the NTV regime. Specifically, the proposed architecture can achieve up to 11 × improvement in variation tolerance and enable up to 113 × reduction in the standard deviation of detection accuracy P d e t while incurring marginal degradation in the median detection accuracy.