NBTI Effects Research Articles

Self-heating of stressed VDMOS devices under specific operating conditions

This paper gives insight into the self-heating effects and combination of self-heating and NBTI effects in p-channel power VDMOS transistors. NBTI effects lead to the degradation of device parameters, where threshold voltage (VT) is the most important one, since it directly affects the device's safe operating area and lifetime. Effects were analysed using images from an infrared thermographic camera taken under different drain currents and controlling signal waveforms. Results point out that the self-heating of the previously stressed devices is more emphasized and that it proposes additional limitations in the terms of the device's reliability.

Improved digital performance of hybrid CMOS inverter with Si p-MOSFET and InGaAs n-MOSFET in the nanometer regime

Using extensive numerical analysis we study the digital performance of 30-nm hybrid CMOS inverters comprising Si p-MOSFETs and In0.70Ga0.30As n-MOSFETs in terms of rise time (tr), fall time (tf), propagation delay (td), noise margins high (NMH) and low (NML) of an inverter, and also the oscillation frequency (fosc) of a ring oscillator with and without considering NBTI effects. Our findings show that for a hybrid CMOS inverter, tf and td exhibit 83% and 73% reduction, respectively, while NMH and NML show improvement of 24.4% and 42.2%, respectively, in relation to those found in the Si CMOS inverter at the ratio of widths of p-MOSFET and n-MOSFET equal to 3. fosc of a 3-stage hybrid ring oscillator exhibits 272.5% improvement over its Si counterpart. Our proposed hybrid inverters outperform equivalent Si inverters for digital applications with and without NBTI degradation at more advanced technology node while dissipating marginally higher OFF-state power.

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.

ENGLISH

Digital multipliers are among the most arithmetic functional units in many applications, such as Fourier transform, discrete cosine transforms, and digital filtering. These applications depends on multipliers, if the multipliers are slow, the performance of entire circuits will be reduced. The proposed aging-aware multiplier design is implemented with a novel adaptive hold logic (AHL) circuit. The multiplier is based on variable-latency technique and adjust the AHL circuit to achieve reliable operation using NBTI and PBTI effects The AHL circuit can decide the input patterns require one or two cycles to adjust the judging criteria to ensure the minimum performance degradation after considerable aging occurs. Comprehensive analysis and comparison of the multipliers performance under different cycle periods to show the effectiveness of our proposed architecture. The performance in 16- and 32-bit multipliers, can be easily extended to large designs. It can provide reliable operations even after the aging effect occurs. The Razor flip-flops detect the timing violations and re-execute the operations using two cycles. The architecture will adjust the percentage of one-cycle patterns to minimize performance degradation due to the aging effect. When the circuit is aged, and many errors occur, the AHL circuit uses the second judging block to decide if an input is one or two cycles. The multiplier is adjust the AHL to mitigate performance degradation due to increase delay.

Modeling and PSPICE simulation of NBTI effects in VDMOS transistors

In this paper the results of modeling and simulation of NBTI effects in p-channel power VDMOS transistor have been presented. Based on the experimental results, the threshold voltage shifts and changes of transconductance during the NBT stress have been modeled and implemented in the PSPICE model of the IRF9520 transistor. By predefining the threshold voltage value before the NBT stress, and by assigning the stress time, transfer characteristics of the transistor are simulated. These characteristics are within (1.33?11.25)% limits in respect to the measured ones, which represents a good agreement.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

NBTI and hot carrier effect of SOI p-MOSFETs fabricated in strained Si SOI wafer

Comparative study on NBTI and hot carrier effects of p-channel MOSFETs fabricated by using strained SOI wafer and unstrained SOI wafer has been performed, respectively. It is observed that NBTI and hot carrier degradation are more significant in strained SOI devices compared with unstrained SOI devices. Since the devices fabricated in strained SOI wafer are SiGe free strained devices, the more generation of interface states during gate oxidation is the main cause for enhanced NBTI and hot carrier degradation in strained SOI devices.

A CMOS circuit for evaluating the NBTI over a wide frequency range

In this paper an application specific integrated circuit (ASIC) for evaluating the NBTI effects over a wide frequency is described. The circuit is designed to allow measurements in multiple modes, specifically, DC and AC NBTI, on single pFET and on an inverter. The results indicate that AC NBTI is independent of the frequency in the 1 Hz–2 GHz range. Furthermore, the voltage and the stress time acceleration are identical for both AC and DC NBTI stress.

NBTI Effects in pMOSFETS with TiN/Hf-Silicate Based Gate Stacks

not Available.

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

In this study, the characteristics of DT-pMOSFETs are discussed using the reverse Schottky substrate contacts. With this diode, the DTMOS can be operated at high voltage and temperature. In addition, it exhibited an improved driving current, DIBL, transconductance, and subthreshold slope. The driving current for DTMOS was 20% larger, and was 12 mV improved for DIBL under DTMOS operation. Furthermore, the NBTI effects of DTMOS were also reported for the first time. This is because DTMOS could operate just below 0.7 V of V G due to the junction turn-on behavior. It is interesting to note that the shift of the Δ V TH of pMOSFETs under NBTI measurement was significantly alleviated in the DT operating mode, about 30 mV improved after 10,000 s stressing, due to the alleviated electrical field across the gate oxide which was due to the substrate bias and the threshold voltage adjustment under DTMOS operation.

NbTi機械式PCS開放時のアーク放電特性とアークが超伝導接点接続に及ぼす影響

NbTi機械式PCS開放時のアーク放電特性とアークが超伝導接点接続に及ぼす影響