Native Gates Research Articles

Quantum extreme learning of molecular potential energy surfaces and force fields

Quantum machine learning algorithms are expected to play a pivotal role in quantum chemistry simulations in the immediate future. One such key application is the training of a quantum neural network to learn the potential energy surface and force field of molecular systems. We address this task by using the quantum extreme learning machine paradigm. This particular supervised learning routine allows for resource-efficient training, consisting of a simple linear regression performed on a classical computer. We have tested a setup that can be used to study molecules of any dimension and is optimized for immediate use on NISQ devices with a limited number of native gates. We have applied this setup to three case studies: lithium hydride, water, and formamide, carrying out both noiseless simulations and actual implementation on IBM quantum hardware. Compared to other supervised learning routines, the proposed setup requires minimal quantum resources, making it feasible for direct implementation on quantum platforms, while still achieving a high level of predictive accuracy compared to simulations. Our encouraging results pave the way towards the future application to more complex molecules, being the proposed setup scalable.

Quanto: optimizing quantum circuits with automatic generation of circuit identities

Existing quantum compilers focus on mapping a logical quantum circuit to a quantum device and its native quantum gates. Only simple circuit identities are used to optimize the quantum circuit during the compilation process. This approach misses more complex circuit identities, which could be used to optimize the quantum circuit further. We propose Quanto, the first quantum optimizer that automatically generates circuit identities. Quanto takes as input a gate set and generates provably correct circuit identities for the gate set. Quanto’s automatic generation of circuit identities includes single-qubit and two-qubit gates, which leads to a new database of circuit identities, some of which are novel to the best of our knowledge. In addition to the generation of new circuit identities, Quanto’s optimizer applies such circuit identities to quantum circuits and finds optimized quantum circuits that have not been discovered by other quantum compilers, including IBM Qiskit and Cambridge Quantum Computing Tket. Quanto’s database of circuit identities could be applied to improve existing quantum compilers and Quanto can be used to generate identity databases for new gate sets.

On the practical usefulness of the Hardware Efficient Ansatz

Variational Quantum Algorithms (VQAs) and Quantum Machine Learning (QML) models train a parametrized quantum circuit to solve a given learning task. The success of these algorithms greatly hinges on appropriately choosing an ansatz for the quantum circuit. Perhaps one of the most famous ansatzes is the one-dimensional layered Hardware Efficient Ansatz (HEA), which seeks to minimize the effect of hardware noise by using native gates and connectives. The use of this HEA has generated a certain ambivalence arising from the fact that while it suffers from barren plateaus at long depths, it can also avoid them at shallow ones. In this work, we attempt to determine whether one should, or should not, use a HEA. We rigorously identify scenarios where shallow HEAs should likely be avoided (e.g., VQA or QML tasks with data satisfying a volume law of entanglement). More importantly, we identify a Goldilocks scenario where shallow HEAs could achieve a quantum speedup: QML tasks with data satisfying an area law of entanglement. We provide examples for such scenario (such as Gaussian diagonal ensemble random Hamiltonian discrimination), and we show that in these cases a shallow HEA is always trainable and that there exists an anti-concentration of loss function values. Our work highlights the crucial role that input states play in the trainability of a parametrized quantum circuit, a phenomenon that is verified in our numerics.

Quantum computation of frequency-domain molecular response properties using a three-qubit iToffoli gate

The quantum computation of molecular response properties on near-term quantum hardware is a topic of substantial interest. Computing these properties directly in the frequency domain is desirable, but the circuits require large depth if the typical hardware gate set consisting of single- and two-qubit gates is used. While high-fidelity multipartite gates have been reported recently, their integration into quantum simulation and the demonstration of improved accuracy of the observable properties remains to be shown. Here, we report the application of a high-fidelity multipartite gate, the iToffoli gate, to the computation of frequency-domain response properties of diatomic molecules. The iToffoli gate enables a ~50% reduction in circuit depth and ~40% reduction in circuit execution time compared to the traditional gate set. We show that the molecular properties obtained with the iToffoli gate exhibit comparable or better agreement with theory than those obtained with the native CZ gates. Our work is among the first demonstrations of the practical usage of a native multi-qubit gate in quantum simulation, with diverse potential applications to near-term quantum computation.

Native Two-Qubit Gates in Fixed-Coupling, Fixed-Frequency Transmons Beyond Cross-Resonance Interaction

Fixed-frequency superconducting qubits demonstrate remarkable success as platforms for stable and scalable quantum computing. Cross-resonance gates have been the workhorse of fixed-coupling, fixed-frequency superconducting processors, leveraging the entanglement generated by driving one qubit resonantly with a neighbor’s frequency to achieve high-fidelity, universal controlled- () gates. Here, we use on-resonant and off-resonant microwave drives to go beyond cross-resonance, realizing natively interesting two-qubit gates that are not equivalent to gates. In particular, we implement and benchmark native i, , iSWAP, and b gates; in fact, any SU(4) unitary can be achieved using these techniques. Furthermore, we apply these techniques for an efficient construction of the B gate: a perfect entangler from which any two-qubit gate can be reached in only two applications. We show that these native two-qubit gates are better than their counterparts compiled from cross-resonance gates. We elucidate the resonance conditions required to drive each two-qubit gate and provide a novel frame tracking technique to implement them in Qiskit. Published by the American Physical Society 2024

Quantum Circuit Compiler for a Shuttling-Based Trapped-Ion Quantum Computer

The increasing capabilities of quantum computing hardware and the challenge of realizing deep quantum circuits require fully automated and efficient tools for compiling quantum circuits. To express arbitrary circuits in a sequence of native gates specific to the quantum computer architecture, it is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the quantum circuit framework Pytket. The performance was evaluated for a wide range of quantum circuits and the results show that the gate counts can be reduced by factors up to 5.1 compared to standard Pytket and up to 2.2 compared to standard Qiskit compilation.

Timing-Aware Qubit Mapping and Gate Scheduling Adapted to Neutral Atom Quantum Computing

As a less developed but potential quantum technology, neutral atoms (NA) can provide advantages including higher qubit connectivity, longer-range interactions, and much more native multi-control gates than superconductivity. Long-range interactions, however, prevent parallelism of interacting qubit pairs with their surrounding restriction zones. Therefore, the quantum program cannot be run directly on a neutral atom quantum computer (NAQC) unless compiled. The recent compiling study of NAQC applies simple layer-by-layer scheduling and does not consider the difference in gate duration. To address the above issues, we focus on the qubit mapping and quantum gate scheduling () problem of quantum circuits to meet hardware constraints of superconductivity and even neutral atoms. Our goal is to shorten the execution time to mitigate decoherence noise. We propose a block-game-like abstraction mechanism which is an abstract model of the problem and aware of the duration difference of gates and several other NA characteristics. Based on the abstraction, we propose a heuristic greedy algorithm (HGA) to solve the problem efficiently. To further speed up the execution of the circuit, we embed HGA into a Monte Carlo tree search (MCTS) framework to solve the problem, which consumes more compiling time but achieves a better result. Comparing our MCTS algorithm with the only recent algorithm for NAQC, the average speedup ratio is 1.75× for several quantum circuits collected from RevLib, and 1.18× for circuits from Qiskit Lib.

Exploring the Advantages of Layout Procedure with Fully‐Connected Quantum Computing Technologies

AbstractEven though quantum algorithms are designed using an idealised high‐level quantum circuit description, the execution on real devices must consider the backend physical properties. Contemporary noisy intermediate‐scale quantum (NISQ) computers are characterized by limited inter‐qubit connectivity and an exclusive set of native gates, whose execution is affected by non‐negligible errors and non‐idealities. Quantum compilation, consisting of logic and layout synthesis, aims to recast the original circuit description to the target hardware by solving the coupling‐constraint and to minimize the execution time and the error rate. While a previous article addresses the first phase, the second one is the aim of this manuscript. Currently available layout tools mainly target superconducting technology. This article tries to match the unmet need for a layout synthesis library supporting a wider range of technologies. The most promising algorithms already present in the state of the art are adapted to extend the compatibility to all the supported technologies, and new approaches, which exploit the awareness of the coupling strength in fully‐connected topologies, are proposed. The integrated procedures are benchmarked against IBM's Qiskit and Cambridge Quantum Computing's compilation toolchains, and even though these strategies can be further improved, the results are encouraging.

Hardware-Conscious Optimization of the Quantum Toffoli Gate

While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.

Optimal, hardware native decomposition of parameterized multi-qubit Pauli gates

We show how to efficiently decompose a parameterized multi-qubit Pauli (PMQP) gate into native parameterized two-qubit Pauli (P2QP) gates minimizing both the circuit depth and the number of P2QP gates. Given a realistic quantum computational model, we argue that the technique is optimal in terms of the number of hardware native gates and the overall depth of the decomposition. Starting from PMQP gate decompositions for the path and star hardware graph, we generalize the procedure to any generic hardware graph and provide exact expressions for the depth and number of P2QP gates of the decomposition. Furthermore, we show how to efficiently combine the decomposition of multiple PMQP gates to further reduce the depth as well as the number of P2QP gates for a combinatorial optimization problem using the Lechner–Hauke–Zoller mapping.

Applications and resource reductions in measurement-based variational quantum eigensolvers

We discuss the procedure for obtaining measurement-based implementations of quantum algorithms given by quantum circuit diagrams and how to reduce the required resources needed for a given measurement-based computation. This forms the foundation for quantum computing on photonic systems in the near term. To demonstrate that these ideas are well grounded we present three different problems which are solved by employing a measurement-based implementation of the variational quantum eigensolver algorithm (MBVQE). We show that by utilising native measurement-based gates rather than standard gates, such as the standard controlled not gate (CNOT), measurement-based quantum computations may be obtained that are both shallow and have simple connectivity while simultaneously exhibiting a large expressibility. We conclude that MBVQE has promising prospects for resource states that are not far from what is already available today.

Sample-efficient verification of continuously-parameterized quantum gates for small quantum processors

Most near-term quantum information processing devices will not be capable of implementing quantum error correction and the associated logical quantum gate set. Instead, quantum circuits will be implemented directly using the physical native gate set of the device. These native gates often have a parameterization (e.g., rotation angles) which provide the ability to perform a continuous range of operations. Verification of the correct operation of these gates across the allowable range of parameters is important for gaining confidence in the reliability of these devices. In this work, we demonstrate a procedure for sample-efficient verification of continuously-parameterized quantum gates for small quantum processors of up to approximately 10 qubits. This procedure involves generating random sequences of randomly-parameterized layers of gates chosen from the native gate set of the device, and then stochastically compiling an approximate inverse to this sequence such that executing the full sequence on the device should leave the system near its initial state. We show that fidelity estimates made via this technique have a lower variance than fidelity estimates made via cross-entropy benchmarking. This provides an experimentally-relevant advantage in sample efficiency when estimating the fidelity loss to some desired precision. We describe the experimental realization of this technique using continuously-parameterized quantum gate sets on a trapped-ion quantum processor from Sandia QSCOUT and a superconducting quantum processor from IBM Q, and we demonstrate the sample efficiency advantage of this technique both numerically and experimentally.

Post-selection-free preparation of high-quality physical qubits

Rapidly improving gate fidelities for coherent operations mean that errors in state preparation and measurement (SPAM) may become a dominant source of error for fault-tolerant operation of quantum computers. This is particularly acute in superconducting systems, where tradeoffs in measurement fidelity and qubit lifetimes have limited overall performance. Fortunately, the essentially classical nature of preparation and measurement enables a wide variety of techniques for improving quality using auxiliary qubits combined with classical control and post-selection. In practice, however, post-selection greatly complicates the scheduling of processes such as syndrome extraction. Here we present a family of quantum circuits that prepare high-quality |0⟩ states without post-selection, instead using CNOT and Toffoli gates to non-linearly permute the computational basis. We find meaningful performance enhancements when two-qubit gate fidelities errors go below 0.2%, and even better performance when native Toffoli gates are available.

Benchmarking quantum error-correcting codes on quasi-linear and central-spin processors

We evaluate the performance of small error-correcting codes, which we tailor to hardware platforms of very different connectivity and coherence: on a superconducting processor based on transmon qubits and a spintronic quantum register consisting of a nitrogen-vacancy center in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, native connectivity, gate times, and coherence times. Using a standard error model parameterized for the given hardware, we simulate the performance and benchmark these predictions with experimental results when running the code on the superconducting quantum device. The results indicate that for small codes, the quasi-linear layout of the superconducting device is advantageous. Yet, for codes involving multi-qubit controlled operations, the central-spin connectivity of the color centers enables lower error rates.

Design and integration of single-qubit rotations and two-qubit gates in silicon above one Kelvin

Spin qubits in quantum dots define an attractive platform for quantum information because of their compatibility with semiconductor manufacturing, their long coherence times, and the ability to operate above one Kelvin. However, despite demonstrations of SWAP oscillations, the integration of this two-qubit gate together with single-qubit control to create a universal gate set as originally proposed for single spins in quantum dots has remained elusive. Here, we show that we can overcome these limitations and execute a multitude of native two-qubit gates, together with single-qubit control, in a single device, reducing the operation overhead to perform quantum algorithms. We demonstrate single-qubit rotations, together with the two-qubit gates CROT, CPHASE, and SWAP, on a silicon double quantum dot. Furthermore, we introduce adiabatic and diabatic composite sequences that allow the execution of CPHASE and SWAP gates on the same device, despite the finite Zeeman energy difference. Both two-qubit gates can be executed in less than 100 ns and, by theoretically analyzing the experimental noise sources, we predict control fidelities exceeding 99%, even for operation above one Kelvin.

Generalization in quantum machine learning from few training data

Modern quantum machine learning (QML) methods involve variationally optimizing a parameterized quantum circuit on a training data set, and subsequently making predictions on a testing data set (i.e., generalizing). In this work, we provide a comprehensive study of generalization performance in QML after training on a limited number N of training data points. We show that the generalization error of a quantum machine learning model with T trainable gates scales at worst as sqrt{T/N}. When only K ≪ T gates have undergone substantial change in the optimization process, we prove that the generalization error improves to sqrt{K/N}. Our results imply that the compiling of unitaries into a polynomial number of native gates, a crucial application for the quantum computing industry that typically uses exponential-size training data, can be sped up significantly. We also show that classification of quantum states across a phase transition with a quantum convolutional neural network requires only a very small training data set. Other potential applications include learning quantum error correcting codes or quantum dynamical simulation. Our work injects new hope into the field of QML, as good generalization is guaranteed from few training data.

Error rate reduction of single-qubit gates via noise-aware decomposition into native gates

In the current era of Noisy Intermediate-Scale Quantum (NISQ) technology, the practical use of quantum computers remains inhibited by our inability to aptly decouple qubits from their environment to mitigate computational errors. In this paper, we introduce an approach by which knowledge of a qubit’s initial quantum state and the standard parameters describing its decoherence can be leveraged to mitigate the noise present during the execution of a single-qubit gate. We benchmark our protocol using cloud-based access to IBM quantum processors. On ibmq_rome, we demonstrate a reduction of the single-qubit error rate by 38%, from 1.6 times 10 ^{-3} to 1.0 times 10 ^{-3}, provided the initial state of the input qubit is known. On ibmq_bogota, we prove that our protocol will never decrease gate fidelity, provided the system’s T_1 and T_2 times have not drifted above 100 times their assumed values. The protocol can be used to reduce quantum state preparation errors, as well as to improve the fidelity of quantum circuits for which some knowledge of the qubits’ intermediate states can be inferred. This paper presents a pathway to using information about noise levels and quantum state distributions to significantly reduce error rates associated with quantum gates via optimized decomposition into native hardware gates.

Software mitigation of coherent two-qubit gate errors

Two-qubit gates are important components of quantum computing. However, unwanted interactions between qubits (so-called parasitic gates) can be particularly problematic and degrade the performance of quantum applications. In this work, we present two software methods to mitigate parasitic two-qubit gate errors. The first approach is built upon the Cartan’s KAK decomposition and keeps the original unitary decomposition for the error-free native two-qubit gate. It counteracts a parasitic two-qubit gate by only applying single-qubit rotations and therefore has no two-qubit gate overhead. We show the optimal choice of single-qubit mitigation gates. The second approach applies a numerical optimisation algorithm to re-compile a target unitary into the error-parasitic two-qubit gate plus single-qubit gates. We demonstrate these approaches on the CPhase-parasitic iSWAP-like gates. The KAK-based approach helps decrease unitary infidelity by a factor of 3 compared to the noisy implementation without error mitigation. When arbitrary single-qubit rotations are allowed, recompilation could completely mitigate the effect of parasitic errors but may require more native gates than the KAK-based approach. We also compare their average gate fidelity under realistic noise models, including relaxation and depolarising errors. Numerical results suggest that different approaches are advantageous in different error regimes, providing error mitigation guidance for near-term quantum computers.

Simulating a measurement-induced phase transition for trapped-ion circuits

The rise of programmable quantum devices has motivated the exploration of circuit models which could realize novel physics. A promising candidate is a class of hybrid circuits, where entangling unitary dynamics compete with disentangling measurements. Novel phase transitions between different entanglement regimes have been identified in their dynamical states, with universal properties hinting at unexplored critical phenomena. Trapped-ion hardware is a leading contender for the experimental realization of such physics, which requires not only traditional two-qubit entangling gates, but also a constant rate of local measurements accurately addressed throughout the circuit. Recent progress in engineering high-precision optical addressing of individual ions makes preparing a constant rate of measurements throughout a unitary circuit feasible. Using tensor network simulations, we show that the resulting class of hybrid circuits, prepared with native gates, exhibits a volume-law to area-law transition in the entanglement entropy. This displays universal hallmarks of a measurement-induced phase transition. Our simulations are able to characterize the critical exponents using circuit sizes with tens of qubits and thousands of gates. We argue that this transition should be robust against additional sources of experimental noise expected in modern trapped-ion hardware and will rather be limited by statistical requirements on postselection. Our work highlights the powerful role that tensor network simulations can play in advancing the theoretical and experimental frontiers of critical phenomena.

Simulating the dynamics of braiding of Majorana zero modes using an IBM quantum computer

We preform dynamic state evolution on an IBM quantum computer using a simulation of braiding Majorana zero modes as a benchmark for success. We find the native quantum gates introduce too much noise to observe braiding. Instead, we use Qiskit Pulse to develop scaled 2-qubit quantum gates that better match the unitary time evolution operator and enable us to observe braiding. This paper demonstrates that quantum computers can be used for simulation, and highlights the use of pulse-level control for programming quantum computers and constitutes the first experimental evidence of braiding via dynamical Hamiltonian evolution.