Nanowire Tunnel FETs Research Articles

Orientation Engineering for Improved Performance of a Ge-Si Heterojunction Nanowire TFET

We have theoretically investigated the crystal orientation effects on the direct band-to-band tunneling probability, and the performance of a 5-nm diameter Ge n-channel nanowire tunnel field-effect transistor (FET). Bulk Ge has indirect band gap, and therefore, its application in tunnel FET is not promising. We study the complex band structures of Ge nanowires in different orientations and showthat the (011) Ge nanowire can be a potential candidate for tunneling FET (TFET). The (001) and (111) nanowires exhibit indirect gaps of 1.07 and 0.966 eV, respectively. In the (001) nanowire, the two X valleys project to the 1-D zone edge and form the conduction band minima. The other X valleys project to the zone center at 0.14 eV above the conduction band minimum. The L[111] and L[ $\overline {{1}}\overline {{1}}\overline {{1}}$ ] valleys project to the zone edge and form conduction band minima in the (111) nanowire. On the other hand, the (011) wire has a direct gap of 0.94 eV due to the projection of L[ $1\overline {{1}}1$ ], L[ $1\overline {{1}}\overline {{1}}$ ], L[ $\overline {{1}} 1\overline {{1}}$ ], and L[ $\overline {{1}}11$ ] valleys to the zone center. Among the three orientations, the (011) wire has the smallest area of the imaginary wave vector that directly connects the band edges at zone center. That is, the (011) wire has the highest direct band-to-band tunneling probability, and therefore, it is a potential candidate for TFETs. We simulate a (011)Ge-(011)Si heterojunction cylindrical nanowire TFET. The staggered band alignment at the heterointerface removes the ambipolar characteristics. The smallest action integral of the (011)Ge wire combined with the shorter tunnel path at the heterointerface results in high drive current for both ${V}_{\text {DD}} = {0.6}$ and 0.4 V. However, the turn-ON behavior with ${V}_{\text {DD}} = {0.4}$ V is superior, which suggests that the proposed nanowire TFET is suitable for low power applications.

Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor

We present a simple model to evaluate the sharpness of the band edges for tunnel field-effect transistors (TFETs) by comparing the subthreshold swing and the conductance in the negative differential resistance region. This model is evaluated using experimental data from InAs/InGaAsSb/GaSb nanowire TFETs with the ability to reach a subthreshold swing well below the thermal limit. A device with the lowest subthreshold swing, 43 mV/decade at 0.1 V, exhibits also the sharpest band-edge decay parameter ${E}_{{0}}$ of 43.5 mV although in most cases the ${S} \ll {E}_{{0}}$ . The model explains the observed temperature dependence of the subthreshold swing.

Atomic-Resolution Spectrum Imaging of Semiconductor Nanowires.

Over the past decade, III-V heterostructure nanowires have attracted a surge of attention for their application in novel semiconductor devices such as tunneling field-effect transistors (TFETs). The functionality of such devices critically depends on the specific atomic arrangement at the semiconductor heterointerfaces. However, most of the currently available characterization techniques lack sufficient spatial resolution to provide local information on the atomic structure and composition of these interfaces. Atomic-resolution spectrum imaging by means of electron energy-loss spectroscopy (EELS) in the scanning transmission electron microscope (STEM) is a powerful technique with the potential to resolve structure and chemical composition with sub-angstrom spatial resolution and to provide localized information about the physical properties of the material at the atomic scale. Here, we demonstrate the use of atomic-resolution EELS to understand the interface atomic arrangement in three-dimensional heterostructures in semiconductor nanowires. We observed that the radial interfaces of GaSb-InAs heterostructure nanowires are atomically abrupt, while the axial interface in contrast consists of an interfacial region where intermixing of the two compounds occurs over an extended spatial region. The local atomic configuration affects the band alignment at the interface and, hence, the charge transport properties of devices such as GaSb-InAs nanowire TFETs. STEM-EELS thus represents a very promising technique for understanding nanowire physical properties, such as differing electrical behavior across the radial and axial heterointerfaces of GaSb-InAs nanowires for TFET applications.

Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET

This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium–arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (Ion/Ioff) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (Ioff) is a weak function of dielectric constant, however, the on current (Ion) increases from 1.51 × 10−7 A µm−1 to 1.79 × 10−6 A µm−1 as the dielectric constant increases from SiO2 to La2O3. It was also observed that as the diameter increases, both Ion and Ioff increases. Ion/Ioff ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, Ioff increases causing degradation in Ion/Ioff ratio. Finally, the effect of interface traps was realised on the Ion/Ioff ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, Ioff degrades rapidly by ~3 orders in magnitude.

Low-Frequency Noise in III–V Nanowire TFETs and MOSFETs

We present a detailed analysis of low-frequency noise (LFN) measurements in vertical III-V nanowire tunnel field-effect transistors (TFETs), which help to understand the limiting factors of TFET operation. A comparison with LFN in vertical metal-oxide semiconductor field-effect transistors with the same channel material and gate oxide shows that the LFN in these TFETs is dominated by the gate oxide properties, which allowed us to optimize the TFET tunnel junction without deteriorating the noise performance. By carefully selecting the TFET heterostructure materials, we reduced the inverse subthreshold slope well below 60 mV/decade for a constant LFN level.

Trap-Tolerant Device Geometry for InAs/Si pTFETs

The influence of channel quantization and interface traps on the performance of InAs/Si pTFETs is analyzed, and a device geometry is predicted which is least sensitive to trap-assisted tunneling (TAT). The good agreement between simulated and measured transfer characteristics validates the reliability of the simulation setup. Simulations show that TAT degrades the sub-threshold swing (SS) of the tunnel field effect transistor (TFET) and that channel quantization reduces its ON-current. The same simulation setup is used to find the device geometry which is least susceptible to interface traps. Scaling down the nanowire diameter below 20 nm inhibits TAT at the oxide/InAs interface. Furthermore, aligning the gate edge with the InAs/Si hetero-junction reduces the degradation of the SS caused by TAT at the hetero-interface. In this way, a gate-aligned InAs/Si nanowire TFET with diameter ~20 nm can deliver sub-thermal sub-threshold swing even in the unavoidable presence of oxide- and hetero-interface traps.

Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs

This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 0.3 V has been obtained at room temperature. An I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sub> (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.

Investigation of DC Characteristics in Polysilicon Nanowire Tunneling Field-Effect Transistors

Investigation of DC Characteristics in Polysilicon Nanowire Tunneling Field-Effect Transistors

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .

Single Defect Discharge Events in Vertical-Nanowire Tunnel-FETs

In this paper, we investigate the single defect discharge events in Ge-source n-type vertical nanowire tunnel field effect transistors, by monitoring the relaxation phase which follows bias temperature instability (BTI) stress. Threshold voltage shift induced by single discharge events follows a bimodal Weibull distribution, with the location parameter of the second mode being significantly higher than the first one. Both modes are temperature independent. Based on TCAD simulations, we propose that the second mode is associated with defects located at the source/channel junction close to the channel/oxide interface, while the first mode is ascribed to oxide traps far from the source/channel junction. Although present in smaller numbers, such traps with a larger average impact on the device characteristics are expected to dominate the BTI-induced variability in a large population of nanoscale devices for realistic applications.

Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

Tunneling field-effect transistors (TFETs) are gaining attention because of their good scalability and low leakage current. However, they suffer from low on-state current and severe ambipolar conductivity. To address these issues, in this paper, we have proposed a novel junctionless nanowire TFET with induced source side tunneling realized by a hetero-gate-dielectric (HGD JN-TFET). This approach induces a local dip in the conduction band edge at the tunneling junction leading to an abrupt transition between the on and off-states as well as subthreshold swing (SS) as low as 45mV/dec at low drain voltages. The proposed structure provides Ion of 8.7×10−6A/µm and Ioff of 1.1×10−11A/µm. Also, we have shown that the length of high-k gate insulator as well as its dielectric constant can significantly affect the performance and power efficiency of this device.

On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

The drain bias dependence of tunnel field-effect transistors (TFETs) is examined on the basis of the measured characteristics and device simulation to understand the electrical behavior of TFETs. Our analyses focus on the long-channel silicon-on-insulator (SOI)-based TFETs as a good basis for further studies of short-channel effects, scaling issues, and more complicated device structures, such as multigate or nanowire TFETs. By device simulation, it is revealed that the drain bias dependence of the transfer characteristics of the measured TFETs is governed by two physical mechanisms: the density of states (DOS) occupancy factor, which depends on drain-to-source bias voltage, and channel electrostatic potential, which is limited by the drain bias through strong carrier accumulation. These mechanisms differ from the drain-induced barrier lowering (DIBL) of metal–oxide–semiconductor field-effect-transistors (MOSFETs), and cause a significant impact even in long-channel SOIs. Finally, the obtained insights are successfully implemented in a TFET compact model.

Gate All Around Nanowire TFET with High ON/OFF Current Ratio

The serious thermal management crises in the next generation digital systems due to power dissipation boom are limited by the reduction in supply voltage. Transistors with lower Subthreshold Slopes (SS) are needed for low power systems. Recent years Tunnel Field Effect Transistors (TFETs) are good alternatives for the existing MOSFETs to cope up with the continuous scaling down of device dimensions. TFETs have reduced Short Channel Effects (SCE), low OFF currents (IOFF) and small SS. But, the major drawback of TFETs is their considerably low ON current (ION). The simplest solution to this problem is a Double Gate (DG) structure, instead of a Single Gate (SG), which will provide ION improvement. A Gate All Around (GAA) structure is the ultimate solution for the improvement of IOFF and ION/IOFF current ratio due to its excellent gate coupling. In this paper a GAA nanowire TFET with a channel length of 32 nm having high ION/IOFF ratio is modelled.

Analysis of Ge-Si Heterojunction Nanowire Tunnel FET: Impact of Tunneling Window of Band-to-Band Tunneling Model

Tunnel FET (TFET) has potential applications in the next generation ultra-low power transistor to substitute the conventional FETs. It can offer very steep inverse subthreshold swing slope to maintain a low leakage current, thus it can be very essential for limiting power consumption in MOSFETs. The carriers in TFET transport from source to channel by the band-to-band tunneling (BTBT) mechanisms. To realize high saturation currents of TFET, it critically depends on the transmission probability, TWKB. In indirect semiconductor, such as Si and Ge, the BTBT model is very crucial for designing and predicting the device performance. In this paper, we employed the nonlocal BTBT model applied to three-dimensional Ge-Si heterojunction TFET with gate length 10 nm compare with Si TFET by including quantum effects simulation. The results show that the Ge-Si TFET outperforms Si TFET because of the lower bandgap and larger tunneling windows. BTBT generation rates of Ge-Si TFET are higher than Si TFET in the on-state condition. The highest BTBT generation rates are located in the source and channel junction and its peaks close to the gate dielectric.

Junctionless nanowire TFET with built-in N-P-N bipolar action: Physics and operational principle

In this paper, we present a novel junctionless nanowire tunneling FET (JN-TFET) in which the source region is divided into an n+ as well as a p+ type region. We will show that this structure can provide a built-in n-p-n bipolar junction transistor (BJT) action in the on state of the device. In this regime, tunneling of electrons from the source valence band into the channel conduction band enhances the hole concentration in the p+ source region. Also, the potential in this region is increased, which drives a built-in BJT transistor by forward biasing the base-emitter junction. Thus, the BJT current adds up to the normal tunneling current in the JN-TFET. Owing to the sharp switching of the JN-TFET and the high BJT current gain, the overall performance of the device, herein called “BJN-TFET,” is improved. On-state currents as high as 2.17 × 10−6 A/μm and subthreshold swings as low as ∼50 mV/dec at VDS = 1 V are achieved.

Modelling doping design in nanowire tunnel-FETs based on group-IV semiconductors

The tunnel field-effect transistor (TFET), which utilises the band-to-band tunnelling mechanism for current conduction, provides the ability to achieve extremely low subthreshold swing (<60mV/dec) and very low off-current, thus offering a performance advantage over conventional inversion-mode metal-oxide-semiconductor field effect transistors (MOSFETs) for the ultra-low power and ultra-low voltage operation for the next generation of transistors. In particular, the optimisation of the TFET architecture and material composition is very important because the full potential of the TFET is not yet uncovered. In this work homo- and hetero-structure nanowire TFETs, based on Si, Ge and SiGe materials, have been investigated using device simulation, for the design of source and drain doping profiles, with nanowire diameters down to 5nm.

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a subthermal SS would only be achievable for $D_{\mathrm{ it}} cm $^{-2}$ eV $^{-1}$ at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of $D_{\mathrm{ it}} cm $^{-2}$ eV $^{-1}$ for vertical InAs/Si NW TFETs with larger diameters.

Quantum Simulation Study on Performance Optimization of GaSb/InAs nanowire Tunneling FET

We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using sp3d5s* is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional Schrödinger-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing ( 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic (ISUBON/SUB 100 μA/μm) that broken-gap TFETs normally have.