Gate All Around Nanowire TFET with High ON/OFF Current Ratio

Abstract

The serious thermal management crises in the next generation digital systems due to power dissipation boom are limited by the reduction in supply voltage. Transistors with lower Subthreshold Slopes (SS) are needed for low power systems. Recent years Tunnel Field Effect Transistors (TFETs) are good alternatives for the existing MOSFETs to cope up with the continuous scaling down of device dimensions. TFETs have reduced Short Channel Effects (SCE), low OFF currents (IOFF) and small SS. But, the major drawback of TFETs is their considerably low ON current (ION). The simplest solution to this problem is a Double Gate (DG) structure, instead of a Single Gate (SG), which will provide ION improvement. A Gate All Around (GAA) structure is the ultimate solution for the improvement of IOFF and ION/IOFF current ratio due to its excellent gate coupling. In this paper a GAA nanowire TFET with a channel length of 32 nm having high ION/IOFF ratio is modelled.