Nanowire Field-effect Transistors Research Articles

A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.35\times $ </tex-math></inline-formula> power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications.

Opto Field-Effect Transistors for Detecting Quercetin-Cu2+ Complex.

In this study, we explored the potential of applying biosensors based on silicon nanowire field-effect transistors (bio–NWFETs) as molecular absorption sensors. Using quercetin and Copper (Cu2+) ion as an example, we demonstrated the use of an opto–FET approach for the detection of molecular interactions. We found that photons with wavelengths of 450 nm were absorbed by the molecular complex, with the absorbance level depending on the Cu2+ concentration. Quantitative detection of the molecular absorption of metal complexes was performed for Cu2+ concentrations ranging between 0.1 μM and 100 μM, in which the photon response increased linearly with the copper concentration under optimized bias parameters. Our opto–FET approach showed an improved absorbance compared with that of a commercial ultraviolet-visible spectrophotometry.

Design and Simulation Analysis of Silicon Germanium Nanowire FET for Low Power Applications

Design and Simulation Analysis of Silicon Germanium Nanowire FET for Low Power Applications

Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled Nanowire Field Effect Transistors

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12.5- and 10.6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{G}$ </tex-math></inline-formula> characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathit {k}$ </tex-math></inline-formula> -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{G}$ </tex-math></inline-formula> characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations.

Analysis of Low Frequency Noise in Schottky Junction Trigate Silicon Nanowire FET on Bonded SOI Substrate

In this work, low frequency noise (LFN) in Schottky junction trigate silicon nanowire (SiNW) field-effect transistors (FETs) (SJGFETs) fabricated on bonded silicon on insulator (SOI) substrate is systematically analyzed. The LFN exhibited a typical 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> spectrum and can be well described by the carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model. It was found that CNF is the dominant component of the LFN, while CMF associated with the Coulomb scattering near the buried oxide (BOX)/SiNW channel interface plays an insignificant role. Applying a substrate bias can further modulate the LFN of the SJGFETs, and the effect is ascribed to the nonuniform energy distribution of the BOX/SiNW channel interface traps. Confining current path in the channel bulk away from the interface brought limited gain in terms of LFN performance. Finally, our experimental results suggested a possible transition of CMF mechanism from Coulomb scattering to surface roughness scattering when the current path is pushed away from the BOX/SiNW channel interface to the channel bulk.

Strain Release Enabled Bandgap Scaling in Ge Nanowire and Tunnel FET Application

The cross-sectional scaling-induced electronic property variations of the Ge and Si nanowires are studied numerically. After removing extra atoms from bulk materials to build the nanowires, not only the lateral quantum confinement is enhanced, but also the cross-sectional size will expand due to the breaking of the intrinsic strain balance. Compared with Si, the strain release-induced size expansion is more obvious in the Ge nanowires, shrinking the bandgaps and thus providing another bandgap modulation direction relative to the quantum confinement. At specific sizes, the strain release effect dominates the modulation and reduces the bandgaps of Ge nanowires even below the bulk value, while the reductions in Si nanowires are negligible, enlarging the band offsets of their heterostructures. As an application, the Ge/Si heterostructure tunnel FET (TFET) is designed and the TCAD simulation reveals a subthreshold swing (SS) of 13.8 mV/dec and an ON-state current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$93 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> , three orders of magnitude larger than that using the bulk materials.

Investigation of Common Source Amplifier Circuit using Gate Stack-Based GAA Dopingless Nanowire Field Effect Transistor

Reported work demonstrates the application of common source amplifier circuit using the proposed Gate Stack based Gate All Around Dopingless Nanowire Field Effect Transistor (GS GAA DL NW—FET) structure. Primarily, impact of the gate stack (GS) technique on the conventional Gate All Around Dopingless Nanowire Field Effect Transistor (GAA DL NW—FET) structure is explored. The proposed FET structure resulted in excellent electrostatic control over the channel by incorporating the advantages of GAA architectures and dopingless technique. As transfer characteristics of conventional GAA DL NW—FET have been enhanced with gate stack (SiO2 + high k) technique when employed at dielectric region. A contrast is drawn between both structures in terms of analog parametric analysis which resulted in improved ION of 30.6 (μA), reduced IOFF of 10−7 (μA) and enhanced ION/IOFF of 6.7 × 107. Linearity analysis were made to examine the distortion less digital communication and a fair comparison is depicted between the structures. CS amplifier circuit application with proposed GS GAA DL NW—FET resulted in improved VOUT with 15.2 dB of gain when compared with GAA DL NW—FET based CS amplifier which stood at 13.9 dB which proves the promising candidature for forthcoming nanoscale circuit applications.

COVID-19 Detection via Silicon Nanowire Field-Effect Transistor: Setup and Modeling of Its Function.

Biomolecular detection methods have evolved from simple chemical processes to laboratory sensors capable of acquiring accurate measurements of various biological components. Recently, silicon nanowire field-effect transistors (SiNW-FETs) have been drawing enormous interest due to their potential in the biomolecular sensing field. SiNW-FETs exhibit capabilities such as providing real-time, label-free, highly selective, and sensitive detection. It is highly critical to diagnose infectious diseases accurately to reduce the illness and death spread rate. In this work, a novel SiNW-FET sensor is designed using a semiempirical approach, and the electronic transport properties are studied to detect the COVID-19 spike protein. Various electronic transport properties such as transmission spectrum, conductance, and electronic current are investigated by a semiempirical modeling that is combined with a nonequilibrium Green’s function. Moreover, the developed sensor selectivity is tested by studying the electronic transport properties for other viruses including influenza, rotavirus, and HIV. The results indicate that SiNW-FET can be utilized for accurate COVID-19 identification with high sensitivity and selectivity.

Analytical model based estimation of line edge roughness induced [formula omitted] variability in nanowire FETs

The line edge roughness (LER) is one of the most dominant sources of variability in sub 10 nm technology node devices such as FinFET and Nanowire FET (NWFET). Earlier, analytical models of LER based threshold voltage (VT) variability on FinFET have been comprehensively explored. However, the analytical modeling front for NWFET is still an open challenge. Specifically, the previous FinFET inspired analysis used a cross-sectional area-equivalent circular diameter as effective diameter (Deff). The Deff defines the local VT for a cross-section that enables a percolation based VT estimation for the NWFET. In this work, we show that minimum local diameter (Dmin) is a better predictor. Dmin captures the quantum confinement locally more accurately in the highly scaled NWFETs of interest to enable accurate percolation. The model is tested for LER infused NWFET structures and shows an excellent match against the well-calibrated Sentaurus TCAD deck with the RMS error less than 1.5 mV. The model is 5×105 times computationally efficient in comparison to conventional TCAD simulations. Moreover, the proposed Dmin based analytical model is 2.3× better in terms of accuracy and 10× faster as opposed to the state-of-the-art (i.e. Deff based model). Such analytical models can be integrated in BSIM CMG platform to enable device scaling study and its impact on circuit level performance predictions.

Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping

In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p+-i-n+ silicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel. The SiNW RFET features simple device design, symmetrical electrical characteristics in the n- and p-channel operation modes using p+-i-n+ diode characteristics, and both operation modes exhibit high ON/OFF ratios (∼106) and high ON currents (∼1 μA μm−1). The proposed device is demonstrated experimentally using a fully CMOS-compatible top-down processes.

Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling

In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

Polycrystalline Silicon Nanowire Field Effect Transistor Biosensors for SARS-CoV-2 Detection

Disease detection and monitoring play a critical role in the ongoing COVID-19 pandemic. A comprehensive detection platform that enables early virus detection can effectively stem the spread of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2). In this study, a polycrystalline silicon nanowire field-effect transistor (NWFET) was developed to detect the spike protein of SARS-CoV-2. The NWFET were fabricated through the application of sidewall spacer etching to maintain a nanowire diameter of less than 100 nm. The on–off current ratio of the transistor reached 106, and its subthreshold swing was 125 mV/decade, indicating the transistor’s strong attributes and stability. The biosensor based on this transistor reached a sensitivity of 59 mV pH−1 when used to test solutions with a pH value ranging between 6 and 9. We employed the biosensor in the detection of the SARS-CoV-2 spike protein, and the results revealed that the characteristic curve gradually shifted toward the left as the antigen of spike protein progressively increased in concentration. The limit of detection was estimated to be 0.51 ag ml−1. The results of the real-time testing of the spike protein were also successful, verifying the performance and applicability of the biosensor as a rapid screening tool for SARS-CoV-2.

Single β-Ga2O3 nanowire back-gate field-effect transistor

In this work, a normally-on single-monocrystal β-Ga2O3 nanowire (NW) back-gate field-effect transistor (FET) has been demonstrated by transferring metal-organic chemical vapor deposition-grown β-Ga2O3 NWs on sapphire onto SiO2(300 nm)/p +-Si substrate. When the gate voltage (V G) exceeds −14 V, the device is pinched off, with an on/off ratio greater than 108 and a drain leakage current density as low as ∼7.34 fA. The maximum field-effect carrier mobility for these n-doped single β-Ga2O3 NW FETs reaches ∼62.2 cm2 (V s)−1. A prompt degradation in the on/off ratio for these β-Ga2O3 NW back-gate FETs is observed as the operation temperature increased up to 400 K. With strong evidence, the temperature-dependent degradation in the performance is determined by the activation of self-trapped holes and intrinsic vacancy-related defects, both of which would lead to a rapid increase in the channel leakage current at high temperatures.

Rational Design of Field-Effect Sensors Using Partial Differential Equations, Bayesian Inversion, and Artificial Neural Networks.

Silicon nanowire field-effect transistors are promising devices used to detect minute amounts of different biological species. We introduce the theoretical and computational aspects of forward and backward modeling of biosensitive sensors. Firstly, we introduce a forward system of partial differential equations to model the electrical behavior, and secondly, a backward Bayesian Markov-chain Monte-Carlo method is used to identify the unknown parameters such as the concentration of target molecules. Furthermore, we introduce a machine learning algorithm according to multilayer feed-forward neural networks. The trained model makes it possible to predict the sensor behavior based on the given parameters.

Twisted Light-Induced Photocurrent in a Silicon Nanowire Field-Effect Transistor

Light can possess orbital angular momentum (OAM), in addition to spin angular momentum (SAM), which offers nearly infinite possible values of momentum states, allowing a wider degree of freedom for information processing and communications. The OAM of light induces a selection rule that obeys the law of conservation of angular momentum as it interacts with a material, affecting the material's optical and electrical properties. In this work, silicon nanowire field-effect transistors are subjected to light with OAM, also known as twisted light. Electrical measurements on the devices consequently reveal photocurrent enhancements after incrementing the OAM of the incident light from 0ℏ (fundamental mode) to 5ℏ. Such a phenomenon is attributed to the enhancements of the photogating and the photoconductive effects under the influence of the OAM of light, the underlying mechanism of which is proposed and discussed using energy band diagrams. With these observations, a strategy for controlling photocurrent has been introduced, which can be a realization of the application in the field of optoelectronics technology.

Acrylamide Hydrogel-Modified Silicon Nanowire Field-Effect Transistors for pH Sensing.

In this study, we report a pH-responsive hydrogel-modified silicon nanowire field-effect transistor for pH sensing, whose modification is operated by spin coating, and whose performance is characterized by the electrical curve of field-effect transistors. The results show that the hydrogel sensor can measure buffer pH in a repeatable and stable manner in the pH range of 3–13, with a high pH sensitivity of 100 mV/pH. It is considered that the swelling of hydrogel occurring in an aqueous solution varies the dielectric properties of acrylamide hydrogels, causing the abrupt increase in the source-drain current. It is believed that the design of the sensor can provide a promising direction for future biosensing applications utilizing the excellent biocompatibility of hydrogels.

ASAP5: A predictive PDK for the 5 nm node

We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the semiconductor industry has adopted to address scaling challenges, improve reliability and performance. These include contact over active gate (COG), fully self-aligned vias (FSAVs), single diffusion breaks (SDBs), and cobalt interconnects. We discuss implications of these changes in the context of standard cell and static random access (SRAM) bit cells. Interconnect modelling is improved and incorporates the effects of metal fill and barrier geometry on line resistivity. Different metal fill and barrier configurations are compared to determine the PDK interconnect stack. We discuss design rule assumptions for the key layers. The PDK uses horizontal nanowire field-effect transistors (NWFETs) for better ON and OFF-state performance. The transistor compact models are calibrated to the 3-D technology computer-aided design (TCAD) simulation results.

Design and Fabrication of Electrostatically Formed Nanowire Gas Sensors With Integrated Heaters

This work reports on the design and fabrication of planar gas sensors with membrane structure to allow in-situ heating capabilities crucial for enhancing gas sensing performances. The sensors are virtual nanowire field-effect transistor (FET) type devices, referred to as electrostatically formed nanowire (EFN) sensors. This work describes the design, fabrication, and performance of a 2 mm X 2 mm chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$850 ~\mu \text{m}$ </tex-math></inline-formula> diameter, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.5 ~\mu \text{m}$ </tex-math></inline-formula> thick membrane. The design has been analyzed using finite element simulations (FEM) and verified experimentally. The thermal efficiency of the heated membrane is found to be 10 mW to reach 400 °C, which is better than most of the reported membrane-based sensors. To improve sensitivity and for broader functionality, the sensing surface, unlike reported in most designs, is at the bottom of the membrane. The technology allows system on chip (SoC) integration and further can be used for the fabrication of handheld battery-operated gas detectors. [2021-0248]

Si nanowire Bio-FET for electrical and label-free detection of cancer cell-derived exosomes

Exosomes are highly important in clinical diagnosis due to their high homology with their parental cells. However, conventional exosome detection methods still face the challenges of expensive equipment, low sensitivity, and complex procedures. Field effect transistors (FETs) are not only the most essential electronic component in the modern microelectronics industry but also show great potential for biomolecule detection owing to the advantages of rapid response, high sensitivity, and label-free detection. In this study, we proposed a Si nanowire field-effect transistor (Si-NW Bio-FET) device chemically modified with specific antibodies for the electrical and label-free detection of exosomes. The Si-NW FETs were fabricated by standard microelectronic processes with 45 nm width nanowires and packaged in a polydimethylsiloxane (PDMS) microfluidic channel. The nanowires were further modified with the specific CD63 antibody to form a Si-NW Bio-FET. The use of the developed Si-NW Bio-FET for the electrical and label-free detection of exosomes was successfully demonstrated with a limit of detection (LOD) of 2159 particles/mL. In contrast to other technologies, in this study, Si-NW Bio-FET provides a unique strategy for directly quantifying and real-time detecting exosomes without labeling, indicating its potential as a tool for the early diagnosis of cancer.