Nanotube Field-effect Transistors Research Articles

Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering

The silicon nanotube field effect transistor (FET) is a tubular structure and has an inner gate and outer gate to control the channel. In this paper, the performance of a junctionless silicon nanotube FET is optimized using inner and outer gate engineering through 3D numerical TCAD simulations. The performance of the optimized devices is enhanced in terms of ON current (ION), OFF current (IOFF), and $$\frac{{I_{{{\text{ON}}}} }}{{I_{{{\text{OFF}}}} }}$$ ratio. Appropriate work function and gate dielectric choices are suggested for the inner and outer gates to obtain optimized devices. The lowest IOFF and highest $$\frac{{I_{{{\text{ON}}}} }}{{I_{{{\text{OFF}}}} }}$$ ratio are obtained for devices with high inner and outer gate permittivity along with low inner and outer gate work function. Also, the highest ION is obtained for the device with the highest inner and outer gate dielectric permittivity with low outer and inner gate work function. The device optimized for ION (98.6% increase compared to reference device) with the corresponding IOFF better than the reference device can be used for high-power applications.

Split gated silicon nanotube FET for bio‐sensing applications

A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (ION) and the threshold voltage (Vth) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive simulations have been done using the SILVACO ATLAS. Sensitivity analysis has been carried out by considering half-filled and full-filled nanogaps with the neutral or charged biomolecules inside the cavity. Significant sensitivity and excellent reduction in short-channel effects has been observed in proposed biosensor.

Photosensitive Complementary Inverters Composed of n‐Channel ReS2 and p‐Channel Single‐Walled Carbon Nanotube Field‐Effect Transistors

For robustness on security and ultralow power consumption for Internet of Things (IoT) sensors, including ultraminiaturization for high chip density, 2D multilayered ReS2 field‐effect transistors (FETs) combined with photoinsensitive single‐walled carbon nanotube (SWNT) FETs are demonstrated for application in light‐to‐frequency (LTF) conversion circuits. Herein, multilayered ReS2 FETs with a direct bandgap (≈1.5 eV) have discernible photoresponsivity of ≈17 A W−1 for red and ≈128 A W−1 for green, respectively, with photodetectivity (≈109 Jones), leading to excellent operation for photosensitive inverters, partly associated with the photoinsensitive SWNT FETs for p‐channel devices. Moreover, the electrical parameters for photosensitive complementary inverters, according to different wavelengths in the dark and under, red (λR = 660 nm), green (λG = 530 nm), and blue (λB = 450 nm) light, are experimentally extracted, and their SPICE simulation‐based validation on working principles of ring oscillators (ROs) is confirmed under light illumination. More impressively, ultralow power consumption for the proposed scheme is achieved due to both the direct bandgap and the large‐energy bandgap, as compared with conventional multilayered MoS2 FET‐based photosensitive inverters, rationally validating the promising opportunity for applications in the envisioned IoT sensor systems.

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1-xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET- reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (Eg) are extracted by using MedeA tool’s VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco’s Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (ID-VGS ) and output (ID-VDS) characteristics have been intensively studied and parameters including ION /IOFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (VTH) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and ION/ IOFF ratio 7.17e + 06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology

Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

Optimization of carbon nano tube field-effect transistors (CNTFET) and compare them to CMOS silicon

In this paper, a brief review of CNT carbon nanotube transistors will be explained and then the optimization methods will be discussed. Details of AC and DC transistor CNFET and Characteristics of CNFET at high temperature also shows that unlike MOSFET flo below the threshold for this type of component temperature is reduced, thus using CNFET at high temperatures can be more quickly and less leakage current is achieved. Processes for the synthesis of CNT are not complete, a subject of controversy in the field fluctuations of density in CNT growth, as well as an analysis of the credit CNFET because sway density of CNT could lead to complete failure CNFET, so to evaluate it, and we later CNFET applications in comparison with CMOS logic circuits using the latest research, we'll CNFET.

Balanced XOR/XNOR Circuits using CNTFET

In this work, a standard design methodology in different logic styles using Carbon Nano Tube field effect transistor is proposed to construct Balanced XOR/XNOR circuit. The Proposed methodology is build on different basic cells to optimize area, power dissipation and delay. The circuits for Balanced XOR/XNOR can be designed with selecting a Elementary basic cell including two independent inputs and two complementary outputs. The basic cell is then combined with various correction and optimization techniques to build a perfect XOR/XNOR circuit to avoid weak zero and week one at the output. Simulation results of the proposed circuits shows better performances in terms of delay, power and PDP. The proposed circuits are evaluated using cadence virtouso.

Analysis of CNTFET Performance in Sequential Device Using Shift Register for Low Power Applications

Nanotechnology has touched the post silicon era where the MOSFET has touched its least scaling value according to Moore’s law. Further lowering in the technology nodes had bring out Short channel effects that are reflected in reliability issues to electronic components which we could visualize in our day today activities. The alternative and the best replacement for CMOS technology is Carbon Nano Tube Field Effect Transistors (CNTFET). These Carbon nanotubes because of their distinctive nature in structural, electrical and mechanical properties will be the building blocks for future Nano electronics. This work focused on design and analysis of Sequential logic devices using CNTFET and comparative analysis with CMOS performance. For Sequential device analysis, we considered Shift register as these forms the basic building block of memory devices. These devices helps in storage or in transfer of binary data. For designing Shift registers we proposed Pulsed latches rather than the regular flip-flops as they consume more power. The design has been implemented in both CNTFET and CMOS technologies for 32nm technology node. The comparative findings show that our suggested job has better Power, Delay and Power Delay Product performance.

Systematic design of CNTFET based OTA and Op amp using gm/ID technique

This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio ($$g_{m}/I_{D}$$) technique for low voltage and low power applications. As square law model failed to produce exact behavior in short channel devices as well as moderate and weak inversion behavior of the transistor. Therefore, $$g_{m} / I_{D}$$ methodology is used to design analog circuits in short channel devices to overcome the shortcomings of square law models. Also, the design using $$g_{m} / I_{D}$$ methodology does not consider the inversion region of the transistor like square law equations. The $$g_{m} / I_{D}$$ methodology is a well-established technique for CMOS analog IC design but CMOS has continuous width while CNTFET width is discrete and depends on different parameters like number of tubes, pitch and diameter of the carbon nanotube. Therefore, there is a need of a design methodology to design analog circuits using CNTFETs. Circuit performance has been investigated extensively using HSPICE simulation.

Channel length scaling of over 100% biaxially stretchable carbon nanotube transistors

Deformable field effect transistors (FETs) are needed for future technologies such as stretchable electronics. We have previously integrated buckled networks of polymer-sorted semiconducting carbon nanotubes and buckled layers of an ion gel dielectric onto elastomeric substrates to create FETs with a channel length of 100 μm that are biaxially stretchable. However, the channel length scaling behavior of this type of FET has not yet been investigated. Of particular concern is the viability of this device architecture when the channel length is reduced below 10 μm, approaching the characteristic buckling length-scale. Here, we fabricate and test buckled nanotube FETs with channel lengths of 8, 17, and 31 μm. We find that the buckling length-scale decreases as the channel length is reduced and that devices at all channel lengths are viable, demonstrating a field-effect mobility of >5 cm2 V−1 s−1 and an on/off ratio of >104, with stability up to 100% biaxial elongation without degradation of performance. A biaxially stretchable inverter is also demonstrated. These findings are important because smaller and higher conductivity FETs that are deformable are needed for next-generation technologies such as stretchable, high-resolution displays and sensors.

Biomembrane-Modified Field Effect Transistors for Sensitive and Quantitative Detection of Biological Toxins and Pathogens.

The efforts of detecting bioactive targets with complex, dynamic, and unknown molecular profiles have inspired the development of various biosensor platforms. Herein, we report a cell-membrane-modified field effect transistor (FET) as a function-based nanosensor for the detection and quantitative measurement of numerous toxins and biological samples. By coating carbon nanotube FETs with natural red blood cell membranes, the resulting biomimetic nanosensor can selectively interact with and absorb broad-spectrum hemolytic toxins regardless of their molecular structures. Toxin-biomembrane interactions alter the local charge distribution at the FET surface in an ultrasensitive and concentration-dependent manner, resulting in a detection limit down to the femtomolar (fM) range. Accurate and quantitative measurements are enabled via a built-in calibration mechanism of the sensor, which overcomes batch-to-batch fabrication variations, and are demonstrated using three distinct toxins and various complex bacterial supernatants. The measured signals of bacterium-secreted proteins correlate linearly with the actual bacterial numbers, making the biosensor a nontraditional approach to rapidly detecting bacterial concentrations without a need to count bacterial colonies.

A chemodosimeter-modified carbon nanotube-field effect transistor: toward a highly selective and sensitive electrical sensing platform.

We present a carbon nanotube-field effect transistor (CNT-FET) biosensor which first implements the chemodosimeter sensing principle in CNT nanoelectronics. We experimentally illustrate the specific molecular interplay that the cysteine-selective chemodosimeter immobilized on the CNT surface can specifically interact with cysteine, which leads to the chemical transformation of the chemodosimeter. Since the chemical transformation of the chemodosimeter can disrupt the charge distribution in the vicinity of the CNT surface, the carrier equilibrium in CNT might be altered, and manifested by the conductivity change of CNT-FET. The real-time conductance measurements show our biosensor is capable of label-free, rapid, highly selective and ultrasensitive detection of cysteine with a detection limit down to 0.45 fM. These results first verify the signaling principle competency of chemical transformation of the chemodosimeter in CNT electronic sensors. Combined with the advantages of the highly selective chemodosimeter and sensitive CNT-FET, the excellent performance of our sensor indicates its promising prospect as a valuable tool for developing highly sensitive and selective sensing platforms in practical application.

Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation

In this paper, electrostatic doped Tunnel carbon nano tube field effect transistor(ED-Tunnel CNTFET) is proposed. Additional gates in the source and drain regions draw an appropriate doping profile, which avoids the most severe issues: the tradeoff between screening and low Fermi energy in Tunnel CNTFETs and the deactivation of dopants in nanoscale transistors with conventional doping. ED-Tunnel CNTFET shows better results over conventional Tunnel CNTFET in terms of ION/IOFF ratio and subthreshold slope (SS). ED-Tunnel CNTFET is investigated for various performance parameters using Nano ViDES device simulator. The simulation results of drain current characteristics at different polarity gates (PGs) bias, drain voltages, diameters of CNT and channel lengths have been extracted. The SS value of ED-Tunnel CNTFET as low as 24 mV/dec at 0.1 V drain voltage for 20 nm channel length and 1 nm channel thickness has been achieved. The device shows improved ION/IOFF ratio and very low SS value demonstrated the potential of proposed device for switching and memory applications.

HPV Sensing by CNTFET Array Nanobiosensor.

Women life is threatened by the cervical cancer each time worldwide. The cervical cancer high grade pre cancer is due to HPV E6 and E7 agents. Nano materials show a key role in medical analysis and action. CNTs (Carbon Nano Tube) have very unique electrical and mechanical properties which are useful in the bio-application. The conventional based biosensors can be improved by CNT based biosensors with respect to sensitivity, selectivity and simple in operation. In comparison with the silicon transistors, CNTFET (Carbon Nano Tube Field Effect Transistor) nano device takes less power and performs faster. The research paper covers working of CNTFET based nano biosensor to detect cervical cancer antibody. 4 x 4 CNTFET sensor array is designed to detect antibody variations on CNTFET gate. The sensor current varied from 4.286 µA to 15.435 µA for gate voltage varied from 0.2 V to 1.06 V. The improved 64 CNTFET based biosensor performs better in sensing the analyte of different concentrations.

DISC-FETs: Dual Independent Stacked Channel Field-Effect Transistors

We experimentally demonstrate a 3D field-effect transistor (FET) architecture leveraging emerging nanomaterials: Dual Independent Stacked Channel FET (DISC-FET). DISC-FET is comprised of two FET channels vertically integrated on separate circuit layers separated by a shared gate. This gate modulates the conductance of both FET channels simultaneously, although the stacked channels are independent, i.e., n-type or p-type with separate source and drain terminals separately accessed via routing. This 3D FET architecture enables new opportunities for area-efficient 3D circuit layouts. The key to enabling DISC-FET is low temperature processing to avoid damaging lower-layer circuits during upper-layer circuit fabrication. As a case study, we use carbon nanotube (CNT) FETs (CNFETs), since they can be fabricated at low temperature (e.g., ${V}_{\textsf {OUT}}$ ) range of 94% of the supply voltage ( ${V}_{\textsf {DD}}$ ) for input voltage ( ${V}_{\textsf {IN}}$ ) ranging from 0 V to ${V}_{\textsf {DD}}$ . 2) output gain (maximum value of - $\Delta {V}_{\textsf {OUT}}/\Delta {V}_{\textsf {IN}})$ of 6.3. 3) logic gate-level hysteresis of 2.4% ${V}_{\textsf {DD}}$ , measured as the difference in ${V}_{\textsf {IN}}$ at which ${V}_{\textsf {OUT}}={V}_{\textsf {DD}}$ /2 between forward and reverse sweeps of ${V}_{\textsf {IN}}$ . All statistics are averaged over 500 NOR2 gates measured with ${V}_{\textsf {DD}} = \textsf {1}$ V. This letter highlights the potential of 3D integration not only for enabling new 3D system architectures but also new 3D FET architectures and 3D circuit layouts.

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

ABSTRACTIn this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.

Reconfigurable NanoFETs: Performance Projections for Multiple-Top-Gate Architectures

In nanowire or nanotube field-effect transistors (nanoFETs) electrostatic doping can be induced by electrical fields originating from multiple independent gates. Therefore, nanoFETs are predestined to explore reconfigurability. Solving the coupled nonlinear Poisson and drift-diffusion differential equations for the three-dimensional electrostatic potential and the one-dimensional channel charge, respectively, we predict the performance of four different reconfigurable (R) nanoFET geometries. The investigated architectures compass FETs with one (1G), two (2G), and three top-gate (3G) terminals with a moderate channel length of half a micrometer. Therefore, the theoretically investigated R-nanoFETs can be manufactured at low costs, allowing to test the performance projections claimed in this paper. The 2G R-nanoFET proved to be the most versatile architecture when no application specific optimization is attempted. However, all considered geometries offer interesting properties. Shortening the program gate with the drain simplifies the local routing and only slightly diminish the performance. A smaller footprint 1G R-nanoFET delivers comparable intrinsic gains at the cost of increased static power dissipation. Finally, a 3G R-nanoFET enables additional dynamic configuration options and faster on/off switching due to a control gate positioned at an increased distance to other metallic contacts.

Carbon nano tube field effect transistor based BBL-PTL full adders with level restorer structures

Full Adder (FA) is an important component not only in arithmetic circuits, but also in designing and development in all types of processors. The performance parameter of the one-bit full adder has been implemented to increase the speed of the system. In this paper two Carbon Nano Tube Field Effect Transistor (CNTFET) based level restorers are introduced to the sum circuit of the branch-based logic and pass transistor (BBL-PT) full adder. The proposed level restorers eliminate the existence of voltage step which is presented in the conventional full adder [1]. T.V.Rao et. al proposed level restorer circuits that have used +1.2 V supply rail voltage [2]. By using these level restorers, we could able to achieve good delay performance. The proposed 1-BIT full adder is graded high as it has less power consumption with the conventional 1-BIT full adders. The performance of the proposed CNTFET based BBL-PT FA with new level restorer structures are examined using Cadence with 32 nm CNTFET technology files with a supply rail voltage of +0.8 V.