To extend the scalability of the logic transistor beyond the 3-nm process, the architecture of the metal-oxide-semiconductor field-effect transistor (MOSFET) has changed from FinFET to gate-all-around FET (GAAFET). In addition, to continue the scaling of MOSFET further, various concepts of nanosheet architecture devices, including GAAFET, Forksheet FET, and Complementary FET, have been vigorously researched. To fabricate nanosheet devices, releasing Si channels via selective etching of Si1-xGex- to Si-layer is a key process. However, during the selective etching of Si1-xGex- to Si-layer, simultaneous etching of Si- with Si1-xGex-layer is inevitable. Therefore, protecting the Si-layer while selective etching of the Si1-xGex-layer is a major challenge to acquire uniform channel layers (i.e., Si-layers). In this study, to protect the Si-layer during the selective wet etching of Si1-xGex- to Si-film, we came up with an idea based on the concept of selective chemisorption of polymers on Si- rather on Si1-xGex-film. Functional groups of polymers can chemisorb onto the Si surface, followed by building the hindrance layer that prohibits the etching of Si-film. Thus, we tested the effect of polymer type additives in selective wet etching of Si1-xGex- to Si-film depending on the functional groups (carboxylic group, amine group, alcohol group, etc.) and the molecular weight. To characterize the etching amount of the Si-film during the selective wet etching of Si1-xGex- to Si-film, the wet etching of epitaxially grown 3-periods of Si1-xGex/Si multilayer on Si substrate was performed followed by high-resolution transmission electron microscopy (HR-TEM) analysis. When using a specific type of polymer additive during wet etching, the etching amount of Si-film was >0.5 nm within 2 minutes, while that using without any additive was ~0.8 nm within 2 minutes, indicating that polymer type additive can produce the hindrance layer successfully onto Si-film preventing the etching of Si-film. The HR-TEM images depending on polymer types and mechanism of protecting Si-film during the selective wet etching of Si1-xGex- to Si-film will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022475, Development of wet Etchant capable of high selection etching in microprocesses below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) References [1] Lee, Seung-Jae, et al. "Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm." Chemical Engineering Journal 475 (2023): 146257.
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