Nanoscale MOS Transistors Research Articles

Phase Noise Reduction in LC VCO’s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FoM}}_{A}$ </tex-math></inline-formula> , is 209 dBc/Hz.

TCAD Simulation of Dose Radiation Effects in Sub-100-nm High-κ MOS Transistor Structures

The sub-100-nm CMOS process with a high-κ gate dielectric is one of the key technologies for the fabrication of digital, analog, and RF VLSI circuits and on-chip systems. The influence of ionizing radiation on 45-nm MOS transistors with a high-κ dielectric fabricated using the bulk-silicon and SOI technologies is simulated. Effects induced by the substitution of SiO2 with a high-κ dielectric are noted. The processes of selection and tuning of physical models for the simulation of high-κ MOS transistors in the Sentaurus TCAD are outlined. A set of new physical semiempirical models introducing the dependence of radiation-sensitive parameters (carrier lifetime, carrier mobility, charge density in the bulk of SiO2 and HfO2 and at the HfO2/Si interfaces) on the irradiation dose is developed. Nanoscale bulk and SOI MOS transistors with a high-κ dielectric are simulated. It is demonstrated that an increase in the drain current after irradiation in nanoscale SOI structures is induced by the charge accumulation in the side oxide. An acceptable fit between the simulation results and the experimental data is obtained. The simulation results confirm that the leakage current is suppressed (compared to common MOS transistors with SiO2) in sub-100-nm MOS transistors with a high-κ dielectric. However, the other important parameters of sub-100-nm MOS transistors with a high-κ dielectric are more sensitive to ionizing radiation.

Power and Noise Optimization Techniques of RF Active Inductor Using Multi-Finger Gate Transistors

In this paper, an optimization technique for active inductor circuit forward noise, size area, and power dissipation is proposed through careful selection of the number of gate fingers N f of a nanoscale MOS transistor. According to simulation results, the application of supply voltage scaling and multi-gate finger transistor techniques can therefore introduce simultaneously a reduction in power consumption around 60% (from 3.35 to 1.32 mW) and a minimization in noise performance at 2 GHz from 3.15 to 2.1 ɳV/√Hz with a small size area and wide tuning range.

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length=90nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.

Complete Circuit Level Random Variation Models of Nanoscale MOS Performance

In this research, the complete analytical circuit level models of random variations in large and small signal parameters of any nanoscale MOS transistor have been proposed. Both triode and saturation regions have been explored. This research has been performed based upon the up to dated nanoscale regime MOS equations with the inclusion of all leading sources of variations instead of only threshold voltage variation. The proposed models have been verified at the nanometer level by using the Monte Carlo SPICE simulations and the Kolmogorov-Smirnof goodness of fit tests. These models are very accurate since they can fit the Monte Carlo based distribution with as high as 99% confidence. Obviously, they eliminate the gap between the circuit level and physical level design since the mismatches in the circuit level parameters can be now analytically formulated in terms of the physical level ones. So, the physical level causes and their relationships with the resulting circuit level mismatches can be revealed. Beside, the proposed models can also be expected to be the potential mathematical foundations for implementating the Electronic CAD cell libraries of the nanoscale MOS transistors. Hence, these models have been found to be efficient for the statistical/variability aware design of various CMOS analog/mixed signal circuits and systems in the nanoscale regime.

Pseudospectral Methods for the Efficient Simulation of Quantization Effects in Nanoscale MOS Transistors

This paper presents an in-detail investigation of the possible advantages related to the use of the pseudospectral (PS) method for the efficient description of the carrier quantization in nanoscale n- and p-MOS transistors. To this purpose, we have implemented, by using both the finite-difference (FD) and PS methods, self-consistent Schrödinger-Poisson solvers for both a 2-D hole gas described by a <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</b> · <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</b> Hamiltonian (suitable for p-MOSFETs) and a 1-D electron gas in the effective-mass approximation (for n-type fin-shaped FETs and nanowire FETs). The PS and FD methods have been systematically compared in terms of the CPU time and the number of discretization points by monitoring not only the subband energies in the low-dimensional carrier gas but also the calculation of some scattering matrix elements that are critically important for the transport modeling. Our results indicate a remarkable reduction in the CPU time for the PS method with respect to the FD method, which makes the PS method very attractive for the modeling of the carrier quantization in nanoscale MOSFETs.

Monte Carlo Simulation of III–V Material-Based MOSFET for High Frequency and Ultra-Low Consumption Applications

High-mobility III-V heterostructures are emerging and very promising materials likely to fulfil high-speed and low-power specifications for ambient intelligent applications. The main objective of this work is to theoretically explore the potentialities of MOSFET based on III-V materials with low bandgap and high electron mobility. First, the charge control is studied in III-V MOS structures using a Schrödinger-Poisson solver. Electronic transport in III-V devices is then analyzed using a particle Monte Carlo device simulator. The external access resistances used in the calculations are carefully calibrated on experimental results. The performance of different structures of nanoscale MOS transistor based on III-V materials is evaluated and the quasi-ballistic character of electron transport is compared to that in Si transistors of same gate length.

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50 nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.

Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors

The subthreshold radio-frequency (RF) characteristics of multi-finger nanoscale MOS transistors were studied by using the measured scattering (s) parameters. Small-signal circuit parameters were determined based on a simplified small-signal equivalent circuit model. We found that besides the source and gate resistances, most of the parameters such as the channel resistance, drain inductance and intrinsic capacitance are found to be significantly different to those in the saturation mode of operation. The subthreshold channel resistance increases and the drain inductance decreases as the finger number increases because of the more significant charge transport along the finger boundaries. In addition, the channel resistance can be governed by the drain-induced barrier lowering in a transistor with very short gate length. The equivalent intrinsic capacitance of the small-signal equivalent circuit is governed by the substrate resistance and capacitance which make the parameter extraction more difficult.

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.

TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling

The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parameter and performance fluctuations in highly scaled nanometer technologies, resulting in a negative average threshold voltages shift, a subthreshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current due to LER-induced inhomogeneous channel potential. The characteristics of the average off-state leakage current and the threshold voltage uncertainty as a function of technology scaling provide a useful guideline for advanced gate patterning process and demand much tighter control of LER less than 3-5 nm for a successful CMOS scaling into deep nanometer scale physical gate length regime below 50 nm.

Two-dimensional quantum mechanical simulation of charge distribution in silicon MOSFETs

A solver for the two-dimensional (2-D) Schrodinger equation based on the k-space representation of the solution has been developed and applied to the simulation of 2-D electrostatic quantum effects in nano-scale MOS transistors. This paper presents the mathematical framework of the simulator, addresses the related accuracy and efficiency problems, and discusses the simulations performed to validate it. Furthermore, the 2-D quantum effects observed in the simulation of charge densities in tens-hundreds nanometer scale MOS structures are described.