Abstract
In this paper, an optimization technique for active inductor circuit forward noise, size area, and power dissipation is proposed through careful selection of the number of gate fingers N f of a nanoscale MOS transistor. According to simulation results, the application of supply voltage scaling and multi-gate finger transistor techniques can therefore introduce simultaneously a reduction in power consumption around 60% (from 3.35 to 1.32 mW) and a minimization in noise performance at 2 GHz from 3.15 to 2.1 ɳV/√Hz with a small size area and wide tuning range.
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