Abstract
The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parameter and performance fluctuations in highly scaled nanometer technologies, resulting in a negative average threshold voltages shift, a subthreshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current due to LER-induced inhomogeneous channel potential. The characteristics of the average off-state leakage current and the threshold voltage uncertainty as a function of technology scaling provide a useful guideline for advanced gate patterning process and demand much tighter control of LER less than 3-5 nm for a successful CMOS scaling into deep nanometer scale physical gate length regime below 50 nm.
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