Nanoscale Metal Oxide Semiconductor Field Effect Transistor Research Articles

Single-Electron Stochastic Resonance Using Si Nanowire Transistors

We demonstrate stochastic resonance (SR) with single electrons (SEs) using nanoscale metal–oxide–semiconductor field-effect transistors (MOSFETs). Input signal applied to a MOSFET modulates SE transport in an average manner based on nonlinear characteristics. On the other hand, an individual SE goes through the MOSFET in a completely random manner, which corresponds to shot noise. SEs transferred to a storage node are counted precisely by the other MOSFET and used as an output signal. The correlation between the input and output signals is improved by taking advantage of extrinsic noise as well as the intrinsic shot noise composed of SEs. It is confirmed that the shot-noise-assisted SR allows fast operation with a simple system. Pattern perception utilizing SR is also demonstrated.

Fluctuations in Electronic Properties of MOS Interface in Nanoscale MOSFETs

Fluctuations in the number, energy level, and carrier capture rate of Si/SiO2 interface traps in small-gate-area metal-oxide-semiconductor field-effect transistors (MOSFETs) containing only a few interface traps have been directly observed. This observation is based on an understanding of charge pumping phenomena and a newly observed phenomenon of on(off)-time-dependent charge pumping characteristics in their rising (falling) portion. It is directly shown from experimental results that the fluctuation in the number of interface traps contained in an individual MOSFET is fairly large, and that there are various interface traps with individual discrete energy levels and carrier capture rates. These fluctuations may have an impact on the variation in device performance of future digital metal-insulator-semiconductor (MIS) devices.

Hybrid Differential Evolution and Particle Swarm Optimization Approach to Surface-Potential-Based Model Parameter Extraction for Nanoscale MOSFETs

A set of semiconductor device model and parameters bridges the communities between circuit design and chip fabrication. In this article, we present an intelligent extraction technique for obtaining a set of optimal model parameters of the surface-potential-based PSP model for the sub-45-nm metal-oxide-semiconductor field effect transistors (MOSFETs). The proposed algorithm combines the standard velocity and position update rules in a particle swarm optimization (PSO) algorithm, and the operations of differential mutation and probability crossover from a differential evolution method. This differential approach can increase the diversity of the population and help particles escape from the local optimal solutions. In addition, the adopted fitness function considers not only the error of the I − V curves, but also their first derivatives. Compared with conventional engineering extraction strategy, the hybrid method extracts 14 DC parameters simultaneously for sub-45-nm N-MOSFET devices. The best accuracy and interesting computational efficiency are obtained by several testing cases.

A compact quantum statistical model for the ballistic nanoscale MOSFETs

AbstractWe develop an analytical quantum statistical model for nanoscale metal‐oxide‐semiconductor field‐effect transistors (MOSFETs). The model describes transport both in the scattering‐limited and ballistic regimes. The expression for the channel current is derived with the Keldysh nonequilibrium Green's function technique. The obtained quantum statistical current expression reduces to the semiclassical one in the absence of scattering. The model indicates that in nanoscale devices the scattering processes become dependent on the bias voltages. The calculated results for the I–V characteristics are in good agreement with the experimental results in the case of a 70 nm MOSFET. The model includes a minimal number of fitting parameters and it can be used in the design of ultra large‐scale integrated circuits.

The channel mobility degradation in a nanoscale metal–oxide–semiconductor field effect transistor due to injection from the ballistic contacts

The ballistic mobility degradation is shown to originate from nonstationary (transient) transport in response to the ohmic electric field. The source and drain reservoirs launch electrons into the channel with injection velocity transiting the channel with finite ballisticity defined as the probability of a collision-free flight. The distinction is made between the ballistic mean free path and that present in a long channel. The results are in excellent agreement with those obtained from Monte Carlo procedures and experiments.

Threshold voltage modeling in (100), (110) and (111) oriented nanoscale MOSFET substrates

An analytical model for the inversion layer quantization for nanoscale - Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with different crystallographic substrate orientations, such as (100), (110) and (111) has been developed. The threshold voltage analysis has been studied using the quantum inversion charge model under three substrate orientations. The results indicate a significant impact of crystal orientation on the threshold voltage and the inversion charge density. The results have also been compared with the numerically reported results and show good agreement.

One-by-one trap activation in silicon nanowire transistors

Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges becoming trapped and de-trapped. However, as a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs, a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and propose a new low-frequency-noise theory for nanoscale FETs. We show that the Coulomb repulsion between electronically charged trap sites prevents the activation of several traps simultaneously. This effect induces a noise reduction of more than one order of magnitude. It decreases when the electron density in the channel is increased due to the electrical screening of traps. These findings are technologically useful for any FET with a short and narrow channel.

Direct Observation of Fluctuations in the Number and Individual Electronic Properties of Interface Traps in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

Fluctuations in not only the number but also the individual electronic properties of interface traps in small-gate-area metal–oxide–semiconductor field-effect transistors (MOSFETs) containing just a few interface traps have been directly observed. This observation is based on an understanding of a newly observed phenomenon in the charge pumping characteristics, i.e., on-time (or off-time)-dependent charge pumping characteristics. It is shown that the fluctuation in the number of interface traps contained in an individual MOSFET is fairly large, and that there are various interface traps with individual carrier capture rates. These fluctuations may have an impact on the variation in threshold voltage of future digital metal–insulator–semiconductor devices.

Modeling and simulation of electronic structure, material interface and random doping in nano-electronic devices

The miniaturization of nano-scale electronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. Modeling and simulation of this class of problems have emerged as an important topic in applied and computational mathematics. This work presents mathematical models and computational algorithms for the simulation of nano-scale MOSFETs. We introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential of the nano-electronic device. This framework enables us to put microscopic and macroscopic descriptions in an equal footing at nano-scale. By optimization of the energy functional, we derive consistently coupled Poisson–Kohn–Sham equations. Additionally, layered structures are crucial to the electrostatic and transport properties of nano-transistors. A material interface model is proposed for more accurate description of the electrostatics governed by the Poisson equation. Finally, a new individual dopant model that utilizes the Dirac delta function is proposed to understand the random doping effect in nano-electronic devices. Two mathematical algorithms, the matched interface and boundary (MIB) method and the Dirichlet-to-Neumann mapping (DNM) technique, are introduced to improve the computational efficiency of nano-device simulations. Electronic structures are computed via subband decomposition and the transport properties, such as the I–V curves and electron density, are evaluated via the non-equilibrium Green’s functions (NEGF) formalism. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our three-dimensional numerical simulations. For these devices, the current fluctuation and voltage threshold lowering effect induced by the discrete dopant model are explored. Numerical convergence and model well-posedness are also investigated in the present work.

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and is therefore proportional to the trend of ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> . The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing trend is given.

Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications

The interface states have been one of the main reliability concerns for nano-scale metal oxide semiconductor field effect transistors (MOSFETs). Especially, the stress induced interface states generation is very important. For quantitatively clarify, the high-frequency charge pumping technique is presented and it has better accuracy and easier than former charge pumping method, which needs variable rise and fall times of gate pulse. Furthermore, it can reject border traps effect. Using the presented method, the energy distribution of interface states was extracted and the Fowler–Nordheim stress induced energy level of interface states was profiled in pure silicon dioxide and finely engineered remote plasma nitrided oxide. The technique is well suited for investigating the nano-scale MOSFET reliabilities.

Analysis of gate tunnelling currents in nanoscale metal—oxide—semiconductor field effect transistors (MOSFETs) with SiO2 and high-K gate dielectrics

In this paper, an analytical model for gate tunnelling current has been deployed by solving the Schrödinger equation using the Wentzel—Kramer—Brillouin approximation method for a trapezoidal potential barrier. The gate tunnelling current has been computed for direct tunnelling from channel to gate as well as for tunnelling from source drain extension region to gate. The effect of temperature variation on gate tunnelling current with an SiO2 thickness of 4nm down to 1nm has been studied at various gate voltages. Gate tunnelling in the case of high-K gate dielectrics and high-K stacks has also been analysed. In order to study the effect of temperature on gate tunnelling current in SiO2 and in high-K dielectrics, the related parameters have been modelled based on physics. The effect of variation of substrate doping concentration (Na) on gate tunnelling current in an n-type metal—oxide—semiconductor field effect transistor (n-MOSFET) with SiO2 has also been studied These studies have been used to bring out the design margins available in equivalent oxide thickness and Na.

Analytic resolution of Poisson–Boltzmann equation in nanometric semiconductor junctions

The design rules in nanoscale integrated circuits have now reached the depletion regions widths in semiconductors devices. In order to describe the complete behavior of junctions, we present the analytic resolution of Poisson–Boltzmann equation in n–p and n–p–n junctions in thermal equilibrium. The main point of this resolution is the exact determination of the boundary conditions at each n–p interface. In n–p–n junction, it appears that under a few hundred of nanometers, the positive potential of the n-type region can overlap the negative potential of the p-type region. This result appears in n–p–n (or p–n–p) structures when the intermediate region is less doped in regard to the opposite regions. An illustration in the evolution of nanoscale metal–oxide–semiconductor field effect transistor (MOSFET) is presented.

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) extraction method is also proven by simulated current–voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.

Quantum mechanical effects on heat generation in nano-scale MOSFETs

The Monte Carlo simulation is performed to investigate the quantum mechanical (QM) effects on heat generation in nano-scale metal oxide semiconductor field effect transistors (MOSFETs) by solving the quantum Boltzmann equation. The influence of QM effects both in real space and K space on the heat generation is investigated.

QUANTUM CONFINEMENT EFFECTS IN STRAINED SILICON MOSFETS

In this paper, we have examined the effect of quantum confinement of carriers on the threshold voltage of strained-silicon (s- Si ) nanoscale Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Using results from quantum theory and two-dimensional simulation, we show that strain-induced threshold voltage roll-off in s- Si nanoscale MOSFETs can be overcome by decreasing s- Si layer thickness. Based on our simulation study, we provide an optimization between threshold voltage, strain and s- Si layer thickness.

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices

Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage ( V th) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V th fluctuation on the gate oxide thickness scaling in 16 nm metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO 2 for the 1.2 and 0.8 nm EOTs, Al 2O 3 for the 0.4 nm EOT and HfO 2 for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of V th fluctuations with the gate oxide thickness scaling (using high-κ dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device’s scaling and have potential in the nanoelectronics application.

Stochastic data processing circuit based on single electrons using nanoscale field-effect transistors

A circuit utilizing single electrons is demonstrated at room temperature using a silicon-on-insulator metal-oxide-semiconductor field-effect transistor (MOSFET). Individual electrons randomly passing through the nanoscale MOSFET, which are the origin of shot noise, are monitored by an electrometer in real time. This random behavior of single electrons is used as a random number for a stochastic associative memory for image-pattern matching, in which the most preferable pattern is extracted with the largest probability. The use of electron transport in the MOSFET provides high controllability of the randomness as well as fast generation of random numbers. The present result promises single-electron applications using nanoscale MOSFETs.

Convective scheme solution of the Boltzmann transport equation for nanoscale semiconductor devices

A model for the simulation of the electron energy distribution in nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) devices, using a kinetic simulation technique, is implemented. The convective scheme (CS), a method of characteristics, is an accurate method of solving the Boltzmann transport equation, a nonlinear integrodifferential equation, for the distribution of electrons in a MOSFET device. The method is used to find probabilities for use in an iterative scheme which iterates to find collision rates in cells. The CS is also a novel approach to 2D semiconductor device simulation. The CS has been extended to handle boundary conditions in 2D as well as to calculation of polygon overlap for polygons of more than three sides. Electron energy distributions in the channel of a MOSFET are presented.