Nanoscale Logic Research Articles

Assembly of silver nanoparticles on nanowires into ordered nanostructures with femtosecond laser radiation.

In this work, we show that well-ordered structures of silver nanoparticles on nanowire substrates can be produced by irradiation with femtosecond (fs) laser pulses at fluences ranging from 10.3 to 15.9 mJ/cm² if the direction of polarization is parallel to the long axis of the nanowire. Experimental results show that a uniformly spaced distribution of nanoparticles is more readily produced on nanowires with lengths L≤2λ, where λ=800 nm is the laser wavelength. The distribution of nanoparticles is found to become less well organized as L≥2λ. Finite element method simulations, combined with experimental observations, indicate that nanoparticles are initially distributed in response to the electric field along the clean Ag nanowire arising from optical excitation. This electric field is responsible for the attraction of nanoparticles to certain locations on the nanowire. We show how a fs-laser-driven assembly of nanoparticles on nanowires can be used in the development of a nanoscale optical logic processor. This method of creating periodic arrays of metallic nanoparticles on nanowire substrates then has many possible applications in electro-optics.

A Customizable Quantum-Dot Cellular Automata Building Block for the Synthesis of Classical and Reversible Circuits.

Quantum-dot cellular automata (QCA) are nanoscale digital logic constructs that use electrons in arrays of quantum dots to carry out binary operations. In this paper, a basic building block for QCA will be proposed. The proposed basic building block can be customized to implement classical gates, such as XOR and XNOR gates, and reversible gates, such as CNOT and Toffoli gates, with less cell count and/or better latency than other proposed designs.

Target-responsive DNA-capped nanocontainer used for fabricating universal detector and performing logic operations.

Nucleic acids have become a powerful tool in nanotechnology because of their controllable diverse conformational transitions and adaptable higher-order nanostructure. Using single-stranded DNA probes as the pore-caps for various target recognition, here we present an ultrasensitive universal electrochemical detection system based on graphene and mesoporous silica, and achieve sensitivity with all of the major classes of analytes and simultaneously realize DNA logic gate operations. The concept is based on the locking of the pores and preventing the signal-reporter molecules from escape by target-induced the conformational change of the tailored DNA caps. The coupling of ‘waking up’ gatekeeper with highly specific biochemical recognition is an innovative strategy for the detection of various targets, able to compete with classical methods which need expensive instrumentation and sophisticated experimental operations. The present study has introduced a new electrochemical signal amplification concept and also adds a new dimension to the function of graphene-mesoporous materials hybrids as multifunctional nanoscale logic devices. More importantly, the development of this approach would spur further advances in important areas, such as point-of-care diagnostics or detection of specific biological contaminations, and hold promise for use in field analysis.

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.

High-κ dielectric breakdown in nanoscale logic devices – Scientific insight and technology impact

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO2-based high-κ dielectrics replacing SiO2 and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness ∼1–2nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

Peculiar transport properties in Z-shaped graphene nanoribbons: A nanoscale NOR gate

A nanoscale logic NOR gate has been theoretically designed by magnetic flux inputs in a Z-shaped graphene nanoribbon composed of an armchair ribbon device sandwiched between two semi-infinite metallic zigzag ribbon leads. The calculations are based on the tight-binding model and iterative Green's function method, in which the conductance as well as current–voltage characteristics of the nanosystem are calculated, numerically. We show that the current and conductance are highly sensitive to both the magnetic fluxes subject to the device and the size of the system. Our results may have important applications for building blocks in the nanoelectronic devices based on graphene nanoribbons.

Integrated all-optical logic discriminators based on plasmonic bandgap engineering

Optical computing uses photons as information carriers, opening up the possibility for ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic devices are indispensible core components of optical computing systems. However, up to now, little experimental progress has been made in nanoscale all-optical logic discriminators, which have the function of discriminating and encoding incident light signals according to wavelength. Here, we report a strategy to realize a nanoscale all-optical logic discriminator based on plasmonic bandgap engineering in a planar plasmonic microstructure. Light signals falling within different operating wavelength ranges are differentiated and endowed with different logic state encodings. Compared with values previously reported, the operating bandwidth is enlarged by one order of magnitude. Also the SPP light source is integrated with the logic device while retaining its ultracompact size. This opens up a way to construct on-chip all-optical information processors and artificial intelligence systems.

Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(001):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the “at will” construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(001):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits

In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX-δ) MOSFETs has been explored by extensive mixed-mode device/circuit simulations. It has been found that, the presence of partial buried oxide and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only suppresses the off-state leakage, short-channel effects, self-heating effect and the process induced threshold voltage variability but also improves the on-state drive current of the devices. Further, although switching energy in the CMOS inverter, NAND and NOR gates based on DSSB SOI and DSSB Pi-OX-δ MOSFETs is almost equal, static power dissipation and propagation delay in the logic gates based on DSSB Pi-OX-δ MOSFET are reduced by ∼75% and ∼20% respectively over the logic gates based on DSSB SOI device. Thus, employing partial buried oxide and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it a suitable candidate for nanoscale CMOS logic circuits.

Site Selective Integration of III–V Materials on Si for Nanoscale Logic and Photonic Devices

Integrating high electron mobility III–V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III–V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III–V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III–V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III–V materials, a concept has been developed comprising the deposition in “v-grooves” with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these “v-grooves”, the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the “v-grooved” trench. This approach offers a promising method of large-scale integration of III–V materials on Si as required for the fabrication of novel logic and photonic devices.

Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

Strained-silicon (Si) has been incorporated into a leading nanoscale logic technology. By means of silicon-germanium (SiGe) alloy stressor embedded in source and drain (S/D) region, the performance of P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) is effectively enhanced. However, when a compressive contact-etch-stop layer (CESL) is combined, the stress interaction and relative impacts of SiGe stressor integrated with CESL on mobility enhancement has been little reported. Therefore, the research performs a three dimensional (3D) stress simulation evaluation based on finite element method (FEM) for PMOSFETs with S/D SiGe stressor and compressive CESL. The proposed simulation methodology is validated as compared with other technological literatures. In additions, the gate width dependency is systematically discussed to explore the stress effects on devices. The analysis results indicate that a -2.6 GPa CESL would continue boosting the stress magnitude on Si channel region except for a gate width smaller than 50 nm. The results are useful for nanoscale transistor while selecting a proper CESL in the manufacturing processes of advanced logic technologies.

Single Nanowire Microscopy and Spectroscopy

Semiconductor nanowires (NWs) have drawn significant attention from the nanotechnology community because of their unique properties that enable new technologies. They have been suggested as elements in next generation field effect transistors,(1) single molecule (bio- or chemical) sensors,(2) nanoscale logic circuitry,(3) lasers,(4, 5) and photodetectors.(6, 7) NWs have even been used in solar cells.(8, 9) However, what is puzzling is that there have been relatively few studies about their optical properties, despite the fact that nanowires are often touted for their interesting optoelectronic properties. In this review, we describe and consolidate what we and others have learned about the optical properties of this important low dimensional system. We begin with ensemble studies about the absorption and emission of CdSe NWs. We then focus on single nanowire microscopies and spectroscopies, which remove intrinsic heterogeneities that obscure detailed yet important NW physics. In particular, we discuss single nanowire absorption cross sections, polarization-dependent excitation/emission anisotropies, time-resolved dynamics, nanowire emission quantum yields, and the extinction spectroscopy of single NWs. Experimental results are presented while key theoretical concepts are outlined to rationalize our findings. Through these studies, we have begun to develop a microscopic picture of NW photophysics that includes electrostatic effects, strongly enhanced in nanoscale materials. We conclude with thoughts about future single nanowire measurements that will likely provide new perspectives about the interplay between electric fields, spectral diffusion, and flickering in 1D NWs and in other related nanosystems.

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array

Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. Specifically, the innate reconfigurability of memristors can be exploited to realize synapses in artificial neural networks. This work focuses on the development of a variation-tolerant training methodology to efficiently reconfigure memristive synapses in a Trainable Threshold Gate Array (TTGA) system. The training process is inspired from the gradient descent machine learning algorithm commonly used to train artificial threshold neural networks, perceptrons. The design and CMOS/Nano implementation of the TTGA system from trainable perceptron based threshold gates is detailed and results are provided to showcase the training process and performance characteristics of the proposed system. Also shown are the results for training a 1T1M (1 Transistor and 1 Memristor) multilevel memristive memory and its performance characteristics.

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.

An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications

In this paper, we have proposed and simulated a new 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) MOSFETs for nanoscale digital circuit applications. The subthreshold electrical properties such as subthreshold current–voltage characteristics, subthreshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed. It has been observed that the DM design can effectively suppress short-channel effects as compared to single material gate structure. The proposed analytical expressions are used to formulate the objective functions, which are the pre-requisite of genetic algorithm computation. The problem is then presented as a multi-objective optimization one where the subthreshold electrical parameters are considered simultaneously. Therefore, the proposed technique is used to search of the optimal electrical and geometrical parameters to obtain better electrical performance of the 10-nm-scale transistor. These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.

Rational growth of branched nanowire heterostructures with synthetically encoded properties and function

Branched nanostructures represent unique, 3D building blocks for the "bottom-up" paradigm of nanoscale science and technology. Here, we report a rational, multistep approach toward the general synthesis of 3D branched nanowire (NW) heterostructures. Single-crystalline semiconductor, including groups IV, III-V, and II-VI, and metal branches have been selectively grown on core or core/shell NW backbones, with the composition, morphology, and doping of core (core/shell) NWs and branch NWs well controlled during synthesis. Measurements made on the different composition branched NW structures demonstrate encoding of functional p-type/n-type diodes and light-emitting diodes (LEDs) as well as field effect transistors with device function localized at the branch/backbone NW junctions. In addition, multibranch/backbone NW structures were synthesized and used to demonstrate capability to create addressable nanoscale LED arrays, logic circuits, and biological sensors. Our work demonstrates a previously undescribed level of structural and functional complexity in NW materials, and more generally, highlights the potential of bottom-up synthesis to yield increasingly complex functional systems in the future.

Neuron dynamics in the presence of1/fnoise

Interest in understanding the interplay between noise and the response of a nonlinear device cuts across disciplinary boundaries. It is as relevant for unmasking the dynamics of neurons in noisy environments as it is for designing reliable nanoscale logic circuit elements and sensors. Most studies of noise in nonlinear devices are limited to either time-correlated noise with a Lorentzian spectrum (of which the white noise is a limiting case) or just white noise. We use analytical theory and numerical simulations to study the impact of the more ubiquitous "natural" noise with a 1/f frequency spectrum. Specifically, we study the impact of the 1/f noise on a leaky integrate and fire model of a neuron. The impact of noise is considered on two quantities of interest to neuron function: The spike count Fano factor and the speed of neuron response to a small steplike stimulus. For the perfect (nonleaky) integrate and fire model, we show that the Fano factor can be expressed as an integral over noise spectrum weighted by a (low-pass) filter function given by F(t,f)=sinc(2)(πft). This result elucidates the connection between low-frequency noise and disorder in neuron dynamics. Under 1/f noise, spike dynamics lacks a characteristic correlation time, inducing the leaky and nonleaky models, to exhibit nonergodic behavior and the Fano factor, increasing logarithmically as a function of time. We compare our results to experimental data of single neurons in vivo [Teich, Heneghan, Lowen, Ozaki, and Kaplan, J. Opt. Soc. Am. A 14, 529 (1997)] and show how the 1/f noise model provides much better agreement than the usual approximations based on Lorentzian noise. The low-frequency noise, however, complicates the case for an information-coding scheme based on interspike intervals by introducing variability in the neuron response time. On a positive note, the neuron response time to a step stimulus is, remarkably, nearly optimal in the presence of 1/f noise. An explanation of this effect elucidates how the brain can take advantage of noise to prime a subset of the neurons to respond almost instantly to sudden stimuli.

All-Photonic Multifunctional Molecular Logic Device

Photochromes are photoswitchable, bistable chromophores which, like transistors, can implement binary logic operations. When several photochromes are combined in one molecule, interactions between them such as energy and electron transfer allow design of simple Boolean logic gates and more complex logic devices with all-photonic inputs and outputs. Selective isomerization of individual photochromes can be achieved using light of different wavelengths, and logic outputs can employ absorption and emission properties at different wavelengths, thus allowing a single molecular species to perform several different functions, even simultaneously. Here, we report a molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder, half-subtractor, multiplexer, demultiplexer, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state. The system demonstrates the advantages of light-responsive molecules as multifunctional, reconfigurable nanoscale logic devices that represent an approach to true molecular information processing units.