High-κ dielectric breakdown in nanoscale logic devices – Scientific insight and technology impact

Abstract

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO2-based high-κ dielectrics replacing SiO2 and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness ∼1–2nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.