Nanoscale Logic Research Articles

2D Molecular Ferroelectric with Large Out‐of‐plane Polarization for In‐Memory Computing

Abstract2D ferroelectric materials with out‐of‐plane polarization are crucial for future nanoscale logic devices due to the increasing demand for energy‐efficient architectures in artificial intelligence. However, only a few 2D out‐of‐plane ferroelectrics are confirmed experimentally. As an important branch of ferroelectrics, organic–inorganic hybrid perovskite ferroelectrics show flexible structures, making them eligible for constructing multifunctional materials. Here, a 2D organic–inorganic hybrid perovskite ferroelectric (6‐BHA)2CdBr4 (6‐BHA is 6‐bromohexylamine) is designed, which crystallizes in polar point group Cc. It experiences the reversal phase transition at 317.8 K and possesses multiaxial ferroelectric properties. More interestingly, it exhibits a large spontaneous polarization value of 3.26 µC cm−2 in out‐of‐plane direction of the film compared with typical 2D ferroelectrics. Moreover, an inverter based on (6‐BHA)2CdBr4 is fabricated, which serves as a proof of concept for the feasibility for logic‐in‐memory devices. This work not only enriches the family of molecular ferroelectrics but also shows the potential to create the next generation of in‐memory computing devices, nanoelectronics devices, and ultra‐high‐density memories.

Voltage-controlled magnetic double-skyrmion states in magnetoelectric elliptical nanostructures by phase-field model

The magnetic skyrmions are promising candidates as information carriers for future energy-efficient spintronic devices (e.g. memory, sensor, logic). Moreover, manipulating elliptically distorted skyrmions can result in a variety of novel functions that differ from those of conventional circular skyrmions. Despite the tremendous prospects, achieving voltage-driven dynamics of the elliptically distorted skyrmions remains a key challenge. Here, we employ dynamical phase-field simulations that consider the strain-mediated magnetoelectric coupling to demonstrate electric field manipulates the dynamic behavior of the elliptically distorted skyrmions. This study finds that the elliptically distorted skyrmions can split into smaller-sized circular skyrmions and reversibly switch between the single domain - single skyrmion and single domain - double skyrmion on elliptical nano-islands. The stabilization of magnetic skyrmions and double skyrmions in multiferroic heterostructures essentially depends on the ratio of the major axis and the minor axis of the elliptical nono-islands. Intriguingly, the operation is non-volatile and exhibits a multistate character. The temporal behavior of energy density variations during the evolution of magnetic domain structures indicates that the electric-field manipulation of skyrmions originates from the competition between elastic, demagnetization, and anisotropic energies. Our work shows that deterministic switching of multiple domain structures on elliptical nano-islands is achievable, indicating the morphology is a new degree of freedom for manipulating the voltage-driven dynamics of skyrmions, providing a novel avenue to develop magnetoelectric coupling-based memory devices, logic devices, sensor devices, etc., at the nanoscale. Impact statementThis research aims to construct a unique multi-state storage device as well as to indicate the morphology is a new degree of freedom for manipulating the voltage-driven dynamics of skyrmions, giving a fresh way to create nanoscale magnetoelectric coupling-based memory, logic, sensor, and other devices.

A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots

A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots

Nanoscale plasmonic combinational logic circuits based on an elliptical resonator.

The half-adder (HA) and half-subtractor (HS) plasmonic combinational logic circuits are explained using a finite element method with a COMSOL software package. The combinational circuits are created using insulator-metal-insulator technology with nanoscale plasmonic structures. In order to achieve an excellent transmission value, the phase angle of optical waves and the position of the control and input ports are the more crucial elements. In this design, the nanoscale combinational circuits are realized at a 35% transmission threshold to distinguish between the logic "0" and logic "1" stand on the interference between the input and control ports with 540n m×250n m dimensions and an 850nm resonant wavelength. The modulation depth, contrast ratio, and insertion loss have 97.38%, and 11.84 and 3.3dB for the HA, and they have 92.38%, and 7.12 and -1.41d B for the HS, respectively.

Hexagonal Close-Packed Polar-Skyrmion Lattice in Ultrathin Ferroelectric PbTiO_{3} Films.

Polar skyrmions are topologically stable, swirling polarization textures with particlelike characteristics, which hold promise for next-generation, nanoscale logic and memory. However, the understanding of how to create ordered polar skyrmion lattice structures and how such structures respond to applied electric fields, temperature, and film thickness remains elusive. Here, using phase-field simulations, the evolution of polar topology and the emergence of a phase transition to a hexagonal close-packed skyrmion lattice is explored through the construction of a temperature-electric field phase diagram for ultrathin ferroelectric PbTiO_{3} films. The hexagonal-lattice skyrmion crystal can be stabilized under application of an external, out-of-plane electric field which carefully adjusts the delicate interplay of elastic, electrostatic, and gradient energies. In addition, the lattice constants of the polar skyrmion crystals are found to increase with film thickness, consistent with expectation from Kittel's law. Our studies pave the way for the development of novel ordered condensed matter phases assembled from topological polar textures and related emergent properties in nanoscale ferroelectrics.

Nanoscale plasmonic logic gates design by using an elliptical resonator.

This study implemented AND, NAND, OR, XOR, NOR, XNOR, and NOT plasmonic logic gates using the finite element method. The all-optical nanoscale logic gates were designed using a single structure based on the technology of insulator-metal-insulator nanoscale plasmonic waveguides. The phase of optical waves and the position of the control and input ports are the most important factors for attaining the optimal transmission value based on interference between the input and control ports. The transmission threshold is 35%, and 850 nm is the operating wavelength. This design creates nanoscale logic gates with a structure dimension of 250nm×250nm. The transmission threshold, modulation depth, contrast ratio, and insertion loss criteria were proposed to evaluate the efficacy of the all-optical gates.

QCA-Based Reliable Fundamental Units for Multiplexer-Demultiplexer and D-Flip-Flop

Quantum-dot cellular automata (QCA) is an advanced nanotechnology. It is applied to delineate nanoscale technology-based logic circuits. It can potentially be replaced the complementary metal oxide semiconductor (CMOS) technology. This paper proposes an optimal and single clocked multiplexer (Mux) circuit, which is made with the help of 12 number of QCA cells in QCA nanotechnology. The proposed Mux circuit is designed in such a way that it can be used easily for the design of the demultiplexer (DeMux) and data flip-flop (DFF) circuits. The proposed Mux is easily converted to DeMux by exchanging the input and output terminals only. The effectiveness of the proposed Mux, DeMux, and DFF is examined with the designs that are similar and available in literature using the QCA Designer-E and QCA Pro tools. The design of the proposed Mux is 89.06% fault-tolerant and has decreased the quantum cost by 62.50% as compared to best reported design. Energy measurement plays a key role when designs are operating at nanoscale level. Energy approximation is done with the help of the QCA Pro tool. The proposed designs are more energy efficient compared to the existing works.

Toward quantum computers by designing a new nano-scale arithmetic & logic unit

Complementary metal-oxide-semiconductor (CMOS) technology is reaching its physical boundaries due to lithographic issues and diminishing scaling advantages. Options to conventional CMOS are becoming more popular, including quantum-dot cellular automata (QCA), nonmagnetic logic, tunneling phase logic, single-electron tunneling, etc. In actuality, QCA adheres to the logic of quantum computers; a quantum computer is a paradigm of how to build a computer. Quantum computers, according to the theory, can execute operations on data using quantum physics concepts such as superposition and entanglement. Quantum characteristics can be utilized to represent data and perform operations on it, which is the underlying premise of quantum computation. As a result, QCA has been proposed as a technology for building circuits at the nano-scale for quantum computing. This technique claims minimal power loss, fast velocity, low occupied area, and great density since the circuits have no electric flows. One of the most crucial and important parts of a microprocessor is the arithmetic logic unit (ALU), which is the key component of the central processing unit (CPU). A unique ALU based on QCA is proposed in this article. In this article, the best AND, OR, XOR, full-adder, and multiplexer circuit are used, which have been examined in detail. The QCADesigner-E program develops and simulates the structure of the recommended ALU. The recommended ALU was also investigated and contrasted with contemporary designs regarding cell counts, area, and temporal complexity. Exactly 185 cells and two clock periods are taken by this design. The number of cells has decreased by 26% in the suggested ALU.

Intensity and phase encoding for realization of integrated Pauli X, Y and Z gates using 2D photonic crystal

Nano-scale all-optical logic gates systems are desirable for the all-optical computing and signal processing applications. All-optical Quantum computing offers excellent computational abilities and lossless operations. The Pauli X, Y and Z gates are vital quantum logic gates for all-optical systems. In this paper, the integrated all-optical Pauli X, Y, Z gate is realized using a square lattice 2D photonic crystal of silicon rods. The phase encoding and intensity encoding techniques have been used simultaneously for the integrated operation. Pauli X, Y, Z logic gate truth table has been verified at the operating wavelength of 1.55 µm.The system offers a linear operation, compact size, low power requirement, and high contrast ratio of 10.4 dB. The footprint of the proposed structure is about 70µm x 70µm and demonstrates a fast response time of 2 ps, bit rate of 0.25 Tbps, which makes it suitable for photonic integrated circuits (PICs).

Nanoscale graphene plasmonics logic gate based on the plasma dispersion effect

Nanoscale graphene plasmonics logic gate based on the plasma dispersion effect

The 20-nm Skyrmion Generated at Room Temperature by Spin-Orbit Torques

The discovery of magnetic skyrmions provides a promising pathway for developing functional spintronic memory and logic devices. Towards the future high-density memory application, nanoscale skyrmions with miniaturized diameters, ideally down to 20 nm are required. Using x-ray magnetic circular dichroism transmission microscopy, nanoscale skyrmions are observed in the [Pt/Co/Ir]15 multilayer at room temperature. In particular, small skyrmions with minimum diameters approaching 20 nm could be generated by the current-induced spin-orbit torques. Through implementing material specific parameters, the dynamic process of skyrmion generation is further investigated by performing micromagnetic simulations. According to the simulation results, we find that both the tube-like Néel-type skyrmions and the bobber-like Néel-type skyrmions can be electrically generated. In particular, the size of the bobber-like Néel-type skyrmions can be effectively reduced by the spin-orbit torques, which leads to the formation of 20 nm Néel-type skyrmions. Our findings could be important for understanding the formation dynamics of nanoscale Néel-type spin textures, skyrmions and bobber in particular, which could also be useful for promoting nanoscale skyrmionic memories and logic devices.

Monolithic Three-Dimensional Tuning of an Atomically Defined Silicon Tunnel Junction.

A requirement for quantum information processors is the in situ tunability of the tunnel rates and the exchange interaction energy within the device. The large energy level separation for atom qubits in silicon is well suited for qubit operation but limits device tunability using in-plane gate architectures, requiring vertically separated top-gates to control tunnelling within the device. In this paper, we address control of the simplest tunnelling device in Si:P, the tunnel junction. Here we demonstrate that we can tune its conductance by using a vertically separated top-gate aligned with ±5 nm precision to the junction. We show that a monolithic 3D epitaxial top-gate increases the capacitive coupling by a factor of 3 compared to in-plane gates, resulting in a tunnel barrier height tunability of 0-186 meV. By combining multiple gated junctions in series we extend our monolithic 3D gating technology to implement nanoscale logic circuits including AND and OR gates.

Ferroelectric nanoscale logic gates by mixed dislocations in SrTiO3

Conventional nanoscale logic gates involve several critical challenges, such as the appearance of leakage currents, and so new approaches to logic calculation devices have been exploited. However, although polarization switching in ferroelectrics has certain advantages in this regard, including nonvolatility, these materials are not leading candidates for logic gates because they disappear at the nanoscale and do not typically allow the two-inputs--one-output operation which is necessary for logic gates. Here, we demonstrate the possibility that ultrasmall ferroelectric nanoscale logic gates can be generated from mixed dislocations in ${\mathrm{SrTiO}}_{3}$. Phase-field simulations show that the unique strain field associated with a mixed dislocation induces a few nanometer polarization spiral, the chirality of which can be switched by electric fields that are both horizontal and vertical to the spiral. Due to this polarization structure, or, and, and not operations can be performed depending on the strength of the electric fields. These results suggest a different means of fabricating ultrathin logic gates, and could potentially lead to energy-efficient ultrahigh logic density devices.

Smart Design of Resistive Switching Memory by an In Situ Current‐Induced Oxidization Process on a Single Crystalline Metallic Nanowire

AbstractResistive switching random access memory (ReRAM) has recently generated significant interest due to its potentials used in nanoscale logic, memory devices, and neuromorphic applications. From the device physics, a uniform dielectric layer is necessary to access as the main switching layer to perform stable resistive switching. This, however, makes the fabrication process more challenging. In this regard, a design of resistive switching memory by an in situ current‐induced oxidization process on a single crystal metallic nanowire (NW) is demonstrated where a single crystal Cu NW is found as the best material with stable switching behaviors after the in situ current‐induced oxidization process. With the in situ current‐induced oxidization process by high current density on the Cu NW, a reversible resistive switching up to 100 cycles with a large ON/OFF ratio of >103 and a low switching voltage of <0.5 V can be obtained. The initial current‐induced oxidation provides a core–shell (Cu2O/Cu) nanowire structure that contributed to the switching properties. The possible switching mechanisms and potential guidelines are systematically proposed. The current work opens up the opportunities to design the ReRAM device with full‐ metallic materials.

Design and analysis of ultra-thin dielectric film embedded nanoscale double-gate MOSFETs for boosting logic performance

This paper presents a systematic study on the performance of double gate (DG)-MOSFETs with an ultrathin embedded dielectric film (DF) at the center of the channel from the source to drain of the device. The numerical simulation results show that for k ≤ 12, the value of ION/IOFF of a 20-nm DF-DG-MOSFET increases with increasing value of DF thickness t reaching a maximum value of about 107 for dielectric constant k = 1, and t = 5 nm whereas, tends to decrease for k > 12. Also, the 20 nm DF-DG-MOSFET with (k = 1, t = 5 nm) shows the lowest subthreshold swing SS of 79 mV/decade and drain induced barrier lowering DIBL of 109 mV/V. However, the intrinsic delay of DF-DG-MOSFET increases with increasing t for k ≤ 12, whereas, decreases as both t and k increase for k > 12 reaching a value of 0.5 ps for (k = 80, t = 5 nm) compared to 0.8 ps for an identical conventional DG-MOSFET. This study, clearly, shows that the performance of DG-MOSFETs can be optimized by wise choice of t and k of an embedded DF and provides guidelines for the design of high performance and low power nanoscale logic devices.

Integrated bioelectronic proton-gated logic elements utilizing nanoscale patterned Nafion.

A central endeavour in bioelectronics is the development of logic elements to transduce and process ionic to electronic signals. Motivated by this challenge, we report fully monolithic, nanoscale logic elements featuring n- and p-type nanowires as electronic channels that are proton-gated by electron-beam patterned Nafion. We demonstrate inverter circuits with state-of-the-art ion-to-electron transduction performance giving DC gain exceeding 5 and frequency response up to 2 kHz. A key innovation facilitating the logic integration is a new electron-beam process for patterning Nafion with linewidths down to 125 nm. This process delivers feature sizes compatible with low voltage, fast switching elements. This expands the scope for Nafion as a versatile patternable high-proton-conductivity element for bioelectronics and other applications requiring nanoengineered protonic membranes and electrodes.

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors

This study presents a novel digital fuzzy approach for image edge detection based on carbon nanotube field effect transistor (CNTFET). The proposed design employs a simple fuzzy rule for digital image edge detection. To investigate the functionality and performance of the proposed fuzzy approach, our results are compared with the MATLAB edge detection operators such as Sobel, Canny, and Prewitt. Based on the simulation results, we demonstrate that the proposed fuzzy approach can be implemented through nanoscale logic gates and provide a reasonable accuracy. The core element of the proposed fuzzy system, implemented with CNTFETs, occupies 0.22 µm2 layout area and consumes 535 nW power consumption. Our results also emphasize the benefits of the Gate-All-Around (GAA) CNTFETs as a potential candidate for nanoscale digital fuzzy image processing applications.

Exotic closure domains induced by oxygen vacancies in compressed BaTiO3 nanofilm

The molecular dynamics method based on the shell model is used to investigate the polarization configuration evolution in compressed BaTiO3 nanofilms with oxygen vacancy lattices of different volume fractions and positions. A clockwise closure domain surrounding a head-to-head domain is observed for a single oxygen vacancy nanofilm. With an increasing oxygen vacancy fraction, the closure domain around the vacancy becomes larger and gradually transforms its rotation direction from clockwise to counterclockwise. Inside the vacancy, except for the head-to-head domain remaining unchanged, the domain changes from a random configuration to a clockwise vortex, and finally to a segmented strip polydomain with 90°- and 180°-domain walls. For a single oxygen vacancy, its location region where the closure domain can occur is obtained, and the model center is a favored site for clockwise vortex nucleation. The closure domain partly changes its orientation if the oxygen vacancy shifts off the model center. In addition, homogeneous closure domains can occur when the vacancy changes its location within a small area. This study demonstrates the feasibility of tuning this kind of closure domain in ferroelectric nanofilms through external loadings and oxygen vacancies. This could be instructive to develop novel nanoscale memories and logic devices.

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults

Radiation-induced single transient faults (STFs) are expected to evolve into multiple transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability evaluation of logic circuits in the presence of MTFs is becoming an important aspect of the design process of deep submicron and nanoscale systems. However, an accurate evaluation of the reliability of large-scale and very large-scale circuits is both very complex and time-consuming. Accordingly, this paper presents a novel soft error reliability calculation approach for logic circuits based on a probability distribution model. The correctness or incorrectness of individual logic elements are regarded as random events obeying Bernoulli distribution. Subsequently, logic element conversion-based fault simulation experiments are conducted to analyze the logical masking effects of the circuit when one logic element fails or when two elements fail simultaneously. On this basis, the reliability boundaries of the logic circuits can efficiently be calculated using the proposed probability model and fault simulation results. The proposed solution can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element. To validate the proposed approach, we have calculated the reliability boundaries of ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits. Statistical analysis and experimental results demonstrate that our method is effective and scalable, while also maintaining sufficiently close accuracy.