Abstract
A requirement for quantum information processors is the in situ tunability of the tunnel rates and the exchange interaction energy within the device. The large energy level separation for atom qubits in silicon is well suited for qubit operation but limits device tunability using in-plane gate architectures, requiring vertically separated top-gates to control tunnelling within the device. In this paper, we address control of the simplest tunnelling device in Si:P, the tunnel junction. Here we demonstrate that we can tune its conductance by using a vertically separated top-gate aligned with ±5 nm precision to the junction. We show that a monolithic 3D epitaxial top-gate increases the capacitive coupling by a factor of 3 compared to in-plane gates, resulting in a tunnel barrier height tunability of 0-186 meV. By combining multiple gated junctions in series we extend our monolithic 3D gating technology to implement nanoscale logic circuits including AND and OR gates.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
