Nanoscale Interconnects Research Articles

Copper Multilayer Interconnection Using Ultravaiolet Nanoimprint Lithography with a Double-Deck Mold and Electroplating

An approach to realizing a two-step interconnection using a double-deck quartz mold based on ultraviolet nanoimprint lithography (UV-NIL) technology and Cu electroplating is discussed. The double-deck mold realizes a two-step simultaneous transcription and a two-step nanoscale interconnection. Nanoscale via and trench array patterns of Cu were formed on a silicon substrate using UV-NIL in combination with electroplating. Imprinted via and trench patterns were simultaneously formed on a photocurable resin by the double-deck mold with a two-step structure. Using this mold, 73 nm metal via and 190 nm metal trench patterns were successfully fabricated by electroplating.

Size-Dependent Resistivity in Nanoscale Interconnects

As the dimensions of conductors shrink into the nanoscale, their electrical conductivity becomes dependent on their size even at room temperature. Although the behavior varies dramatically as temperatures increase from nanokelvins to hundreds of kelvins, the effect is generally to increase the resistivity above that of bulk material. As such, the underlying size-dependent phenomena have become increasingly important as advanced technologies have shifted their focus first from macro- to microscale and more recently from micro- to nanoscale dimensions. Indeed, the size-dependent increase of electrical resistivity that results from electron scattering on external and internal surfaces of copper conductors has already become technology limiting in modern microelectronics. This article summarizes the phenomena that underlie size effects, focusing on conduction in copper lines in particular. Attention is given to describing key innovations in both theoretical and experimental assessments that have significantly modified, facilitated, or advanced understanding.

DNA-templated gold nanowires

We have developed simple methods of reproducibly creating deoxyribonucleic acid (DNA)-templated gold nanowires on silicon. First DNA nanowires were aligned on silicon surfaces. Briefly, modified silicon wafer was soaked in the DNA solution, and then the solution was removed using micropipettes; the surface tension at the moving air–solution interface is sufficient to align the DNA nanowires on the silicon wafer. In another attempt, an aqueous dispersion of sodium azide-stabilized gold nanoparticles was prepared. The nanoparticles aligned double-stranded λ-DNA to form a linear nanoparticle array. Continuous gold nanowires were obtained. The above nanowires were structurally characterized using scanning electron microscopy. The results of the characterizations show the wires to be 57–323 nm wide, to be continuous with a length of 2.8–9.5 μm. The use of DNA as a template for the self-assembly of conducting nanowires represents a potentially important approach in the fabrication of nanoscale interconnects.

Modeling heating effects in nanoscale devices: the present and the future

In this review paper we give an overview on the present state of the art in modeling heat transport in nanoscale devices and what issues we need to address for better and more successful modeling of future devices. We begin with a brief overview of the heat transport in materials and explain why the simple Fourier law fails in nanoscale devices. Then we elaborate on attempts to model heat transport in nanostructures from both perspectives: nanomaterials (the work of Narumanchi and co-workers) and nanodevices (the work of Majumdar, Pop, Goodson and recently Vasileska, Raleva and Goodnick). We use our own simulation results which we have used to examine heat transport in nanoscaling devices to point out some important issues such as the fact that thermal degradation does not increase as we decrease feature size due to the more pronounced non-stationary transport and ballistic transport effects in nanoscale devices. We also point out that instead of using SOI, if one uses Silicon on Diamond technology there is much less heat degradation and better spread of the heat in the Diamond material. We also point out that tools for thermal modeling of nanoscale devices need to be improved from the present state of the art as 3D tools are needed, for example, to simulate heat transport and electrical transport in a FinFET device. Better models than the energy balance equations for the acoustic and optical phonons what we presently use in our simulators are also welcomed. The ultimate goal is to design the tool that can be efficient enough but at the same time can simulate most accurately both electrons and phonons within the particle pictures by solving their corresponding Boltzmann transport equations self-consistently. Investigations in integration of Peltier coolers with CMOS technology are also welcomed and much needed to reduce the problem of heat dissipation in nanoscale devices and interconnects.

Carbon better than copper for nanoscale interconnects

Carbon better than copper for nanoscale interconnects

Improved Electrode Performance of Porous LiFePO4 Using RuO2 as an Oxidic Nanoscale Interconnect

Improved Electrode Performance of Porous LiFePO₄ Using RuO₂ as an Oxidic Nanoscale Interconnect

Innovative Al Damascene Process for Nanoscale Interconnects

A novel chemical vapor deposition (CVD)-Al technique of “bottom-up growth” was developed using methylpyrrolidine alane as a precursor and a (PVD)-TiN/CVD-TiN stacked barrier in a damascene structure. Poor step coverage of PVD-TiN caused an absence of PVD-TiN at the bottom of trenches, resulting in selective Al growth. The new method filled a 40-nm-wide trench (aspect ratio = 7.5) completely and showed robust electrical properties. The lowest line resistance was obtained at a stacked layer of PVD-TiN/CVD-Ru due to the low resistivity of Ru. Furthermore, the fine Al line structure fabricated by the new technique revealed that the Al line structure did not suffer severely from the size effect, which started to affect Cu damascene structures that were 50 nm wide.

Electrical resistivity of polycrystalline Cu interconnects with nano-scale linewidth

The maximum electrical conductivities in polycrystalline Cu interconnects with sub-100nm linewidth were extrapolated from the measured resistivities of the Cu interconnects with various linewidths (100–1000nm) using a Mayadas–Shatzkes (MS) model. These polycrystalline Cu interconnects with TiN cap layers were fabricated by the focused ion beam technique. The scattering parameters by the surface and grain boundary, which were needed to extrapolate the resistivities of the sub-100nm Cu interconnects (using the MS model), were determined to be zero and 0.5, respectively. The result suggested that the grain boundary scattering primarily increased the resistivity of the polycrystalline Cu interconnects. We concluded that large grained Cu interconnects and ultrathin barrier layers were essential to realize low resistance nano-scale Cu interconnects in the future ultralarge scale integration devices.

Dielectrophoretically Controlled Fabrication of Single-Crystal Nickel Silicide Nanowire Interconnects

We report here on applying electric fields and dielectric media to achieve controlled alignment of single-crystal nickel silicide nanowires between two electrodes. Depending on the concentration of nanowire suspension and the distribution of electrical field, various configurations of nanowire interconnects, such as single, chained, and branched nanowires were aligned between the electrodes. Several alignment mechanisms, including the induced charge layer on the electrode surface, nanowire dipole-dipole interactions, and an enhanced local electrical field surrounding the aligned nanowires are proposed to explain these novel dielectrophoretic phenomena of one-dimensional nanostructures. This study demonstrates the promising potential of dielectrophoresis for constructing nanoscale interconnects using metallic nanowires as building blocks.

Surface bismuth removal after Bi nanoline encapsulation in silicon

Recently, several kinds of atomic-scale wires have been reported for nano-scale device and interconnect applications. The Bi nanoline is one of the most promising candidates because of its structural perfection and the capability to be buried in an epitaxial Si layer. A surfactant layer of Bi is necessary for the encapsulation process, and this remains on the sample surface after the burial, but it needs to be removed so that the buried Bi line may be properly characterized by I– V measurements, X-ray diffraction, etc. without perturbations from the surface layer. It is shown by RHEED observation that the thermal desorption is not suitable for this purpose, because the one-dimensional structure of the buried Bi line is disrupted over the same time scale as for removal of the surfactant Bi. Chemical wet etching of the surface layer was found to be a better solution to the removal of the surfactant Bi atoms without destroying the buried Bi lines.

Real-time STM study of inter-nanowire reactions: GdSi 2 nanowires on Si(1 0 0)

We report the co-existence and growth of two different types of GdSi 2 nanowires (NWs) following Gd deposition on the Si(1 0 0) surface. The first NW type is hexagonal and similar in appearance and orientation to that previously reported in the literature. The structure of the second NW type is unknown, but its orientation, thermodynamic stability and surface appearance are consistent with an orthorhombic structure. Real-time high-temperature STM studies show that these new NWs are thermodynamically preferred and in regions where both wires co-exist, they grow at the expense of their hexagonal counterparts. The implications of these observations for nanoscale interconnects is discussed.

Mechanical properties of ultrahigh-strength gold nanowires

Nanowires have attracted considerable interest as nanoscale interconnects and as the active components of both electronic and electromechanical devices. Nanomechanical measurements are a challenge, but remain key to the development and processing of novel nanowire-based devices. Here, we report a general method to measure the spectrum of nanowire mechanical properties based on nanowire bending under the lateral load from an atomic force microscope tip. We find that for Au nanowires, Young's modulus is essentially independent of diameter, whereas the yield strength is largest for the smallest diameter wires, with strengths up to 100 times that of bulk materials, and substantially larger than that reported for bulk nanocrystalline metals (BNMs). In contrast to BNMs, nanowire plasticity is characterized by strain-hardening, demonstrating that dislocation motion and pile-up is still operative down to diameters of 40 nm. Possible origins for the different mechanical properties of nanowires and BNMs are discussed.

DNA-Templated Assembly of Conducting Gold Nanowires between Gold Electrodes on a Silicon Oxide Substrate

Here we report on the DNA-templated self-assembly of conducting gold nanowires between gold electrodes lithographically patterned on a silicon oxide substrate. An aqueous dispersion of 4-(dimethylamino)pyridine-stabilized gold nanoparticles was prepared. These nanoparticles recognize and bind selectively double-stranded calf thymus DNA aligned between the gold electrodes to form a linear nanoparticle array. Continuous polycrystalline gold nanowires are obtained by electroless deposition that enlarges and enjoins the individual gold nanoparticles. The above nanowires were structurally characterized using a range of electron and scanning probe microscopies and electrically characterized at room temperature using a standard probe setup. The results of these characterizations show these wires to be 20 nm high and 40 nm wide, to be continuous between interdigitated gold electrodes with an interelectrode spacing of 0.2 or 1.0 μm, and to possess a resistivity of 2 × 10-4 Ωm. These DNA-templated nanowires, the smallest reported to date, exhibit resistivities consistent with reported findings and current theory. The use of DNA as a template for the self-assembly of conducting gold nanowires represents a potentially important approach to the fabrication of nanoscale interconnects.

Molecular electronics: from devices and interconnect to circuits and architecture

As the dominating CMOS technology is fast approaching a brick wall, new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.

Study of electron-scattering mechanism in nanoscale Cu interconnects

This paper presents a study of electron scattering in damascene-processed Cu interconnects. To understand the leading electron-scattering mechanism responsible for the size effect, Cu interconnects with varying physical widths, 80–750 nm, were made, and their resistivity characterized as a function of temperature, ranging from liquid He temperature (4.2 K) to 500 K. The resulting data suggest that surface scattering, contrary to expectations, was not the primary cause of the size effect observed in this investigation. Surface scattering was found to weaken with decreasing line width. Further analysis leads to the conclusion that a substantial fraction of the size effect originates from impurity content scaling inversely with width in these samples.

Electromigration failure in ultra-fine copper interconnects

This paper presents experimental evidence suggesting that electromigration (EM) can be a serious reliability threat when the dimension of Cu interconnects approaches the nanoscale range. To understand the failure mechanism prevailing in nanoscale Cu interconnects, single-level, 400-µm long interconnects with various effective widths, ranging from 750 nm to 80 nm, were made, EM tested, and characterized in this investigation. The results indicate that interface EM (Cu/barrier) may be the predominant EM mechanism in all line widths. The evidence supporting the active Cu/barrier interface EM includes the fact that the EM lifetime is inversely proportional to the interface area fraction. Microscopic analysis of the failure sites also supports the conclusion of interface EM because voids and hillocks are found at the ends of the test strip, which is not possible if lines fail by grain-boundary EM in the test structure used in this study. In addition, our study finds evidence that failure is assisted by a secondary mechanism. The influence of this factor is particularly significant when the feature size is small, resulting in more uniform distribution of failure time in narrower lines. Although limited, evidence suggests that the secondary factor is probably attributed to pre-existing defects or grain boundaries.

In situ quantum dot growth on multiwalled carbon nanotubes.

The generation of nanoscale interconnects and supramolecular, hierarchical assemblies enables the development of a number of novel nanoscale applications. A rational approach toward engineering a robust system is through chemical recognition. Here, we show the in situ mineralization of crystalline CdTe quantum dots on the surfaces of oxidized multiwalled carbon nanotubes (MWNTs). We coordinate metallic precursors of quantum dots directly onto nanotubes and then proceed with in situ growth. The resulting network of molecular-scale "fused" nanotube-nanocrystal heterojunctions demonstrates a controlled synthetic route to the synthesis of complex nanoscale heterostructures. Extensive characterization of these heterostructures has been performed using scanning electron microscopy (SEM), transmission electron microscopy (TEM), high-resolution transmission electron microscopy (HRTEM), energy-dispersive X-ray spectroscopy (EDS), X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, UV-visible spectroscopy, and X-ray diffraction (XRD).

Optimization of Ultrathin ALD Tantalum Nitride Films for Zero-Thickness Liner Applications

AbstractA metal-organic atomic layer deposition (ALD) tantalum nitride process has been demonstrated for zero-thickness liner applications in advanced copper metallization schemes. Utilizing a commercially available ALD reactor, this process employs a liquid tantalum source (tertbutylimido tris(diethylamido) tantalum—TBTDET) and ammonia as the reactants. Key functionality data addressing the self-limiting nature of ALD film growth with respect to key process parameters including processing temperature and the substrate surface exposures to TBTDET and ammonia have been obtained, leading to the establishment of an optimized ALD processing window. Highly conformal, continuous, and smooth growth over high aspect ratio structures is exhibited, and incubation periods appear to be relatively substrate independent. Preliminary thermal and electrical copper barrier performance testing of the deposited films indicates that they hold promise for use in emerging nanoscale interconnect applications.

Nanoscale control of chain polymerization.

Polymer industries depend on the spontaneous polymerization of molecules into chains in response to an appropriate trigger. We have succeeded in inducing and guiding chain polymerization over tiny distances, initiating and terminating linear propagation at any chosen point to a spatial precision of about 1 nm by using the probe tip of a scanning tunnelling microscope. Being able to exert such fine control over nanoscale fabrication and interconnection should help to take molecular nanoelectronics beyond the present silicon-based-device technology.

In Situ Stem Technique for Characterization of Nanoscale Interconnects During Electromigration Testing

AbstractA technique for observing microstructure and morphology changes during annealing or electromigration of 100 nm-scale and smaller interconnects is presented. The technique is based on dynamic in situ characterization using a UHV field-emission scanning transmission electron microscope (STEM) and can enable full microstructural characterization (images, diffraction patterns and compositions) during electromigration testing. Initial steps in the validation of the approach include in situ electron-beam OMCVD of Al-containing wires and observation of these wires. Although the deposition conditions were not optimized, Al-containing wires, with high edge acuity, thickness uniformity, and with minimum interconnect widths as small as 15 nm have successfully been deposited. In situ imaging of the annealing of 100 nm Al films on 25 nm Si3N4 substrates at 350°C demonstrates that an image resolution of 10 nm should readily be attainable in passivated nanoscale interconnects during electromigration.