Nanoscale Field Effect Diode Research Articles

Superior energy-delay-production in nanoscale field effect diode by embedded doped pockets for digital applications

Superior energy-delay-production in nanoscale field effect diode by embedded doped pockets for digital applications

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Performance Improvement of Nanoscale Field Effect Diode (FED) with Modified Charge Channel: 2D Simulation and an Analytical Surface Potential Model

Performance Improvement of Nanoscale Field Effect Diode (FED) with Modified Charge Channel: 2D Simulation and an Analytical Surface Potential Model

Improved nanoscale field effect diode

To overcome the short channel effects of a regular field effect diode (FED), this paper proposes a novel nanoscale FED. The novel FED has a simple structure that can be fabricated by the standard CMOS process technology. Both regular and novel FEDs are simulated using TCAD tools as a semiconductor drift-diffusion solver. Simulation results show that the novel device can operate properly at nanoscale channel length. The I ON/I OFF ratio of the novel FED is several orders of magnitude higher than of the regular FED.

Nanoscale field effect diode (FED) with improved speed and I ON / I OFF ratio

Field effect diodes (FEDs) are devices that have higher ON current and lower OFF current compared to metal oxide semiconductor field effect transistors in similar dimensions. The modified FED and side contacted FED (S-FED) structures do not turn off for 40 nm channel lengths and shorter by considering the band-to-band tunnelling model. In this study, a new structure of FED with a 25 nm channel is presented. In this structure, the use of isolating oxides and reservoirs in the channel causes improvement in the structural compared to the conventional FED structures. The proposed techniques reduce the tunnelling in the channel. The simulations have been done by using Silvaco TCAD. In the proposed structure, the results show that the OFF current and gate delay are decreased from 1.5 mA to 66.5 nA and 0.103 to 0.033 ps, respectively. Also, compared with the S-FED structure by considering the band-to-band tunnelling model, the knee voltage for the length of the 25 nm channel dropped from 0.8 to 0.4 volts. Furthermore, the I ON / I OFF ratio, which is an important parameter in digital applications, dramatically increases to a magnitude of 10 5 .

Effects of the Spacer Length on the High-Frequency Nanoscale Field Effect Diode performance

The performance of nanoscale Field Effect Diodes as a function of the spacer length between two gates is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 for S-FED as the spacer length between two gates increases whereas this ratio is approximately constant for M-FED. The high-frequency performance of FEDs is investigated and the cut-off frequency of the intrinsic transistor without parasitic capacitance is calculated. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic applications.

Performance simulation of a three-dimensional nanoscale field-effect diode

The modified field effect diode (FED) can provide orders of magnitude larger ratio compared to regular MOSFETs at sub-100 nm channel lengths. However, fabrication of the modified FED requires implantation of very thin and highly doped n- and p-type regions on top of each other, which is a major practical problem to overcome. An improved sub-100 nm channel length 3D configuration of the FED is proposed and simulated using Silvaco TCAD software. Fabrication of this configuration is compatible with a regular CMOS process while providing a larger ION/IOFF ratio. The current–voltage (I–V) characteristics of this structure is obtained and compared with that of a semiconductor-on-insulator MOSFET (SOI-MOSFET) with the same dimensions numerically. Simulation results indicate that the ION/IOFF ratio of the 3D FED is five orders of magnitude larger than that of the comparable SOI-MOSFET.

Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET

The Automatic Gain Control (AGC) systems based on nanoscale Field Effect Diode (FED) and double gate silicon on insulator (SOI) MOSFET are investigated in this paper. Using double gate devices leads to more flexibility in gain controlling, improving performance, and power consumption reduction. Simulation results show these systems have better characteristics in terms of power and band-width in comparison with AGC system based on regular MOSFET. Among proposed alternative structures (SOI-MOS, MOSFET, FED), nanoscale FED is specifically suited for variable gain amplifier circuits in AGC systems which leads to improve performance and reduce power consumption in low-power applications. © IEICE 2010.

A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode

A novel sub-threshold inverter based on nanoscale Field Effect Diode (FED) and a basic static CMOS inverter are investigated in this paper. Simulation results demonstrate that power consumption and Power Delay Product (PDP) of the sub-threshold inverter which is designed with nanoscale FED are 57.9% and 18.21% less than these factors in a comparable CMOS sub-threshold inverter. So the nanoscale FED scheme can provide better power efficiency than standard sub-threshold CMOS inverters.

Low-power variable gain amplifier with wide UGBW based on nanoscale Field Effect Diode

Simulation results are provided for the modified nanoscale Field Effect Diode (FED) used as a variable gain amplifier in automatic gain control systems. Field Effect Diode is similar to regular MOS transistors with the exception of using two gates over the channel region and oppositely doped source and drain. Its current-voltage characteristic results in large gain, low power dissipation and better frequency response compared with automatic gain control systems based on regular CMOS transistors. An added feature is the lack of short channel effects in Field Effect Diodes.

Simulation Results for Nanoscale Field Effect Diode

Using the PISCES-IIb semiconductor drift-diffusion solver, we have simulated the current-voltage (I-V) curve of a nanoscale field-effect diode (FED) with a gate length of 75 nm and a gate oxide thickness of 2 nm. Whereas devices longer than 100 nm provide ION/IOFF ratios that are larger than those of comparable silicon-on-insulator MOSFETs (SOI-MOSFETs), the 75-nm device provides a very poor ION/IOFF ratio. A modified version of an FED is proposed, which provides an ION/IOFF ratio that is an order of magnitude larger than that of a comparable SOI-MOSFET for portions of its I-V curve. It appears that the FED can be considered as a viable structure for some digital circuits at these device lengths, provided that minor modifications are made to the regular CMOS process