Nanometer Regime Research Articles

Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit

High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.

Complex Systems in Phase Space.

The continued reduction of semiconductor device feature sizes towards the single-digit nanometer regime involves a variety of quantum effects. Modeling quantum effects in phase space in terms of the Wigner transport equation has evolved to be a very effective approach to describe such scaled down complex systems, accounting from full quantum processes to dissipation dominated transport regimes including transients. Here, we discuss the challanges, myths, and opportunities that arise in the study of these complex systems, and particularly the advantages of using phase space notions. The development of particle-based techniques for solving the transport equation and obtaining the Wigner function has led to efficient simulation approaches that couple well to the corresponding classical dynamics. One particular advantage is the ability to clearly illuminate the entanglement that can arise in the quantum system, thus allowing the direct observation of many quantum phenomena.

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

SummaryOver the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm2 physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.

Mesoporous Silica Encapsulated Metal-Organic Frameworks for Heterogeneous Catalysis

Encapsulation of metal-organic frameworks (MOFs) with a shell of mesoporous silica can boost overall performance of MOFs, offering versatility for synthetic architecture of integrated nanocatalysts with reactor-like features. Recently, Yu et al. report a green approach to make yolk-shell nanoreactors.

Nanoscale topography, surface charge variation and defect correlation in 2–8 nm thick functional alumina films

In the nanometric regime, alumina films are often deposited by ALD methods yet in industrial applications, sputtered films thinner than 40 nm are used and research into those is sparse. Here, we investigated the nanoscale topography and the electrical properties of films less than 10 nm thick deposited by direct RF magnetron sputtering. Alumina films deposited on Si appeared to be uniform and topographically defect free as evaluated by TEM and AFM. However, their composition varied as a function of thickness as measured by XPS. The films were non-stoichiometric as Al content increased with film thickness. While SSRM measured current profiles did not highlight leakage sites or voids in the films, KPFM measured local charge fluctuations across the films deposited on Si and Au surfaces. The density of fluctuation sites decreased with an increase of alumina thickness. An electrodeposition method identified insulation weak spots in the alumina where Cu growths formed on the alumina surface. The growth mechanisms were investigated by TEM and EDX. The density of growths decreased with increased alumina thickness. Defects in the deposited alumina film are expected to be due to its non-stoichiometric nature causing charge variations, which weaken the films electrical insulating capability.

Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

Performance Evaluation of Silicon-Transition Metal Dichalcogenides Heterostructure Based Steep Subthreshold Slope-Field Effect Transistor Using Non-Equilibrium Green’s Function

With technology invading nanometer regime performance of the Metal-Oxide-semiconductor Field Effect Transistor is largely hampered by short channel effects. Most of the simulation tools available do not include short channel effects and quantum effects in the analysis which raises doubt on their authenticity. Although researchers have tried to provide an alternative in the form of tunnel field-effect transistors, junction-less transistors, etc. but they all suffer from their own set of problems. Therefore, Metal-Oxide-Semiconductor Field-Effect Transistor remains the backbone of the VLSI industry. This work is dedicated to the design and study of the novel tub-type Metal-Oxide-Semiconductor Field-Effect Transistor. For simulation Non-Equilibrium Green’s Function is used as the primary model of simulation. The device is analyzed under different physical variations like work function, permittivity, and interface trap charge. This work uses Silicon-Molybdenum Disulphide heterojunction and Silicon-Tungsten Disulphide heterojunction as channel material. Results for both the heterojunctions are compared. It was analyzed that Silicon-Molybdenum Disulphide heterojunction provides better linearity and Silicon-Tungsten Disulphide heterojunction provides better switching speed than conventional Metal-Oxide-Semiconductor Field-Effect Transistor.

Enhancement of Short Channel Effect and Drain Induced Barrier Lowering in Fin-FET

The essential requirement of any battery-operated and mobile devices like laptops, cellular phones are that they must be small in size, consume less power, fast processing and cheaper expansion. Gordon Moore found in 1965 that the quantity of transistors on a chip will drive to be twofold every year, by manufacturing the portable devices and building circuit on the silicon chip which makes device cost effective. This drop in size of transistor is termed as scaling. Since scaling faces formidable challenges in nanometer regime, successors have been emerged as FinFET’s. They have thin fin or wing like channels enclosed by several gates. Due to many gates the design helps to improve performance and boost energy efficacy. Present work highlights the role of scaling and how scaling improves the speed of the device. The expectation from the scaled device is to consume as low power as possible, effective in costs and less design time. As we make the instrument more portable, complexity in it becomes infinite. Moore’s law supports us to realize the role of scaling to improve circuit performance and make a portable/mobile device. Here, we design 14nm, 10nm and 7nm Triple gate Fin-FET (TG Fin-FET) and investigate the Drain Induced Barrier Lowering (DIBL) and Short Channel Effect (SCE). By scaling the device DIBL and SCE are reduced giving better performance in terms of power and speed.

Scalable Synthesis of Microsized, Nanocrystalline Zn0.9 Fe0.1 O-C Secondary Particles and Their Use in Zn0.9 Fe0.1 O-C/LiNi0.5 Mn1.5 O4 Lithium-Ion Full Cells.

Conversion/alloying materials (CAMs) are a potential alternative to graphite as Li‐ion anodes, especially for high‐power performance. The so far most investigated CAM is carbon‐coated Zn0.9Fe0.1O, which provides very high specific capacity of more than 900 mAh g−1 and good rate capability. Especially for the latter the optimal particle size is in the nanometer regime. However, this leads to limited electrode packing densities and safety issues in large‐scale handling and processing. Herein, a new synthesis route including three spray‐drying steps that results in the formation of microsized, spherical secondary particles is reported. The resulting particles with sizes of 10–15 μm are composed of carbon‐coated Zn0.9Fe0.1O nanocrystals with an average diameter of approximately 30–40 nm. The carbon coating ensures fast electron transport in the secondary particles and, thus, high rate capability of the resulting electrodes. Coupling partially prelithiated, carbon‐coated Zn0.9Fe0.1O anodes with LiNi0.5Mn1.5O4 cathodes results in cobalt‐free Li‐ion cells delivering a specific energy of up to 284 Wh kg−1 (at 1 C rate) and power of 1105 W kg−1 (at 3 C) with remarkable energy efficiency (>93 % at 1 C and 91.8 % at 3 C).

High slew rate circuit for high rigidity friction-drive

In various fields of research and development in the nanometre regime, a rigid and robust positioning device with nanometic resolution is indispensable. Rapid movement of the piezo-element to induce high shear or propulsive impulse has become one of the widely used mechanisms. The piezo-elements used for this impulsive lateral movement often serve as mechanical support of the moving object, and since they tend to be the narrowest path in the mechanical loop, their rigidity is of great importance in implementing a device with high natural frequency and mechanical stability. The paper presents circuitry to drive such piezo-elements with comparatively larger surface area and higher capacitance with high transient current and slew rate. The circuit could drive a capacitive load of 100 nF, corresponding to 90 cm2 of the piezo-element, from 0 to 200 V in 1 μs, with a peak current of up to 100 A.

Architecture of resistive RAM with write driver

As technological advancements are increasing in the world at a faster rate, the need of miniaturization is also growing parallelly. The scaling of existing MOS technology in nanometre regime has caused some limitations such as drastically increase in leakage current, power consumption and some quantum mechanical effects. This paper provides an insight of an alternative technology which makes use of new circuit element called memristor which can be successfully scaled at a lower nanometre regime. This paper proposes a new READ and WRITE circuitry to facilitate an easier read and write operation. The paper illustrates a transmission gate based 2T1M RRAM bit cell which uses memristor as a memory element and subjects it to process, voltage and temperature (PVT) variations with the aim of reflecting the improvement in performance metrices read and write delay along with the read current variability. The SPICE simulation results reflect that the proposed memory cell has a better stability due to its less read current variability against process variation (such as varying oxide thickness) and is robust with minimal variation in read/write delay with respect to the variations in voltage and temperature. The cell depicts shorter read and write delay compared to NAND and NOR CMOS based flash memories and it has 98.72%,94.53% lesser write time when compared to ambipolar transistor-based memory cell and memristor based content addressable memory (MCAM) respectively. The proposed cell also has 72.5% lesser read time compared to MCAM.

A robust wire crossing design for thermostability and fault tolerance in quantum–dot cellular automata

Quantum-dot cellular automata (QCA) present an unconventional computing model in the nanometer regime. The applications in QCA require complex wire crossings between intersectional wires. The existing wire crossing schemes show low fault tolerance or thermal instability. In this paper, a robust wire crossing scheme is proposed by using two opposite clock zones and redundant cells. The thermostability and fault tolerance are illustrated by using statistical analysis and fault simulations with regard to cell undeposition. This paper also presents a new signal distribution network (SDN) using the proposed wire crossings. The layouts of an XOR gate and a full adder are investigated to show the scalability of the proposed designs to circuits for logic functions with various number of inputs. For the proposed wire crossing and SDN, the circuitries of metal wires to provide the electric fields for driving the involved cells in each clock zone are also discussed. The functionalities of these circuits are validated by using QCADesigner.

Process‐induced variability modeling of subthreshold leakage power considering device stacking

SummaryThe dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFET into nanometer regime, and has become a significant component of total IC power dissipation. The issue is further aggravated with the inability to gauge the tolerance of process parameters around their nominal value. Consequently, the drive to improve the static power prediction has enticed accurate and reliable modeling of leakage current, specifically for ultralow power applications. In contrast to gate‐ and band‐to‐band‐tunneling leakages, subthreshold leakage exhibits high susceptibility to process variations and hence has been considered for variability modeling. Fluctuations in the device electrical and geometry parameters result in a wider distribution of subthreshold leakage current. Hence, taking into account stacking effect, an analytical variability model to estimate subthreshold leakage power in subthreshold circuits, in the presence of threshold voltage variations is proposed. Further, the impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model‐generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700 computationally faster than SPICE simulations with mean error being less than 0.19%.

The Strongest Size in Gradient Nanograined Metals.

Conventional polycrystalline metals become stronger with decreasing grain size, yet softening starts to take over at the nanometer regime, giving rise to the strongest size at which the predominate strengthening mechanism switches to softening. We show that this critical size for the onset of softening can be tuned by tailoring grain size gradient, and raising in the gradient shifts the size toward the smaller value. The decrease in the strongest size is prompted by mitigation of grain boundary-mediated softening processes accompanying by enhanced intragranular plastic deformations. We found that the nanograins smaller than 6 nm, mainly involving intergranular sliding in homogeneous structures, reveal anomalous plastic deformation in gradient systems, which is mediated by partial dislocation nucleation, faulting and twinning activated in a gradient stress field. The results on extended dislocation slip and gradient plasticity, stemming from the structure heterogeneity, shed light on an emerging class of heterogeneous nanostructured materials of improved strength-ductility synergy.

Site-selective [2 + 2 + n] cycloadditions for rapid, scalable access to alkynylated polycyclic aromatic hydrocarbons.

Polycyclic aromatic hydrocarbons (PAHs) are attractive synthetic building blocks for more complex conjugated nanocarbons, but their use for this purpose requires appreciable quantities of a PAH with reactive functional groups. Despite tremendous recent advances, most synthetic methods cannot satisfy these demands. Here we present a general and scalable [2 + 2 + n] (n = 1 or 2) cycloaddition strategy to access PAHs that are decorated with synthetically versatile alkynyl groups and its application to seven structurally diverse PAH ring systems (thirteen new alkynylated PAHs in total). The critical discovery is the site-selectivity of an Ir-catalyzed [2 + 2 + 2] cycloaddition, which preferentially cyclizes tethered diyne units with preservation of other (peripheral) alkynyl groups. The potential for generalization of the site-selectivity to other [2 + 2 + n] reactions is demonstrated by identification of a Cp2Zr-mediated [2 + 2 + 1]/metallacycle transfer sequence for synthesis of an alkynylated, selenophene-annulated PAH. The new PAHs are excellent synthons for macrocyclic conjugated nanocarbons. As a proof of concept, four were subjected to alkyne metathesis catalysis to afford large, PAH-containing arylene ethylene macrocycles, which possess a range of cavity sizes reaching well into the nanometer regime. Notably, these high-yielding macrocyclizations establish that synthetically convenient pentynyl groups can be effective for metathesis since the 4-octyne byproduct is sequestered by 5 Å MS. Most importantly, this work is a demonstration of how site-selective reactions can be harnessed to rapidly build up structural complexity in a practical, scalable fashion.

Strain tuned high thermal conductivity in boron phosphide at nanometer length scales - a first-principles study.

Breakdown of Fourier law of heat conduction at nanometer length scales significantly diminishes thermal conductivity, leading to challenges in thermal management of nanoelectronic applications. In this work we demonstrate using first-principles computations that biaxial strain can enhance k at a nanoscale in boron phosphide (BP), yielding nanoscale k values that exceed even the bulk k value of silicon. At a length scale of L = 200 nm, k of 4% biaxially strained BP is enhanced by 25% to a value of 150.4 W m-1 K-1, relative to 120 W m-1 K-1 computed for unstrained BP at 300 K. The enhancement in k at a nanoscale is found to be due to the suppression of anharmonic scattering in the higher frequency range where phonon meanfreepaths are in nanometers, mediated by an increase in the phonon band gap in strained BP. Such a suppression in scattering enhances the meanfreepaths in the nanometer regime, thus enhancing nanoscale k. First-principles computations based on deriving harmonic and anharmonic force interactions from density-functional theory are used to provide detailed understanding of the effect in terms of individual scattering channels.

Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip

In this article, we will present recent advances in VLSI reliability effects with a focus on electromigration (EM) failure/aging effect on interconnects, which is one of the most important reliability concerns for VLSI systems especially at the nanometer regime. One of the most important advances for EM analysis in recent years is the recognition that EM failure analysis can't depend on single wire segment anymore, as done in the traditional Black and Blech's based methods. New generation of EM modeling and design must consider all the wire segments in an interconnect as the hydrostatic stress in those wire segments affect each other. Such recognition bring both challenges and opportunities. We will start with physics-level stress-oriented characterization of EM failure effects and recently proposed three-phase EM models. Then we present a new EM immortality check at the circuit level considering multi-segment interconnects and void saturation volumes. After this, we will present how to accelerate EM aging effects for fast EM validation at the circuit level under normal working conditions using advanced structure-based techniques. Finally, we will present new EM sign-off analysis tool, called EMspice, at the full-chip power grid level considering the interplays between resistance changes from post-voiding processes and current density changes from power grids over the aging process. A number of other relevant works will be reviewed and compared as well.

Linearity Distortion Analysis of III–V and Si Quadruple Gate Field Effect Transistor (QG-FET) for Analog Applications

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET- reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (Eg) are extracted by using MedeA tool’s VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco’s Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (ID-VGS ) and output (ID-VDS) characteristics have been intensively studied and parameters including ION /IOFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (VTH) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and ION/ IOFF ratio 7.17e + 06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

An investigation on a triple material double gate cylindrical gate all around (TMDG-CGAA) MOSFET for enhanced device performance

The present work investigates the Triple Material Double Gate Cylindrical Gate All Around (TMDG-CGAA) MOSFET in the nanometer regime to improve the device performance. Electrical parameters of TMDG-CGAA MOSFET are investigated under varying physical conditions like channel length, channel thickness, oxide thickness, and core diameter. For various parameters like drain current, threshold voltage, DIBL, and transconductance the TMDG-CGAA MOSFETs are evaluated. The comparison has been done among the SG-CGAA MOSFET, DG-CGAA MOSFET, and TMDG-CGAA MOSFET by using the same device parameters. The proposed structure TMDG-CGAA MOSFET has been validated by a device simulator named as 3D ATLAS tool. The device performance enhances by incorporating three materials at the gate electrode in the DG-CGAA MOSFET. In the planar MOSFET devices the SCEs enhances and also the threshold voltage is rolling off due to the reduced potential barrier between source and drain. But in the proposed structure the threshold voltage increases in the nanometer region also due to its cylindrical geometry. The drain current, transconductance also improves in comparison with the SG-CGAA MOSFET and DG-CGAA MOSFET. The SCE like DIBL decreases in the proposed structure. So overall the proposed structure shows better device performance with fast switching and lower cost.