Nanometer Process Research Articles

A numeric investigation of friction behaviors along tool/chip interface in nanometric machining of a single crystal copper structure

The interaction between the tool rake face and the chip is critical to chip morphology, cutting forces, surface quality, and other phenomena in machining. A large body of existing literature on nanometric machining or nano-scratching only considers the overall friction behavior by simply regarding the total force along tool movement direction as the friction force, which is not suitable for describing the intriguing friction phenomena along the tool/chip interface. In this study, the molecular dynamic (MD) simulation is used to model the nanometric machining process of single crystal copper with diamond tools. The effects of three factors, namely, tool rake angle, depth of cut, and tool travel distance, are considered. The simulation results reveal that the normal force and friction force distributions along tool/chip interface for all cases investigated are similarly shaped. It is found that the normal force consistently increases along the entire tool/chip interface when a more negative rake angle tool is used. However, the friction force increases as the rake angle becomes more negative only in the contact area close to the tool tip, and it reverses the trend in the middle of tool/chip interface. Meanwhile, the increase of depth of cut overall increases the normal force along the tool/chip interface, but the friction force does not necessarily increase. Also, the progress of tool into the work material does not change the patterns of normal force, friction force, or friction coefficient distributions to a great extent. More importantly, it is discovered that the traditional sliding model with a constant friction coefficient can be used to approximate the later section of friction distributions. However, no friction model for traditional machining is appropriate to describe the first section of friction distributions obtained from the MD simulation.

Molecular Dynamics Modeling of Nanoscale Machining of Silicon

In this study, the brittle-ductile transition in nanometric machining of mono-crystalline silicon with precise tool specifications and parameter choices is accessed. Due to its brittle nature, silicon material requires a ductile-mode machining for improved surface quality. Molecular dynamics (MD) methods are thus applied to investigate the atomistic reaction at the tool/workpiece surface to clearly expose the ductile transition response of this nanometric process. However, the need for experimental validations to determine the accuracy of these simulation models is essential. This research is particularly concerned with the application of the molecular dynamics simulation approach to the atomistic visualization of the plastic material flow at the tool/workpiece interface during orthogonal cutting. Simulated MD acting force and temperature outputs are evaluated to access the accuracy of the model. This evaluation substantiates the need for additional experimental validation of certain process conditions for verifiable MD results.

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop.

Error Detection and Correction Architecture of Finite State Machine State Transition for Nanometer Process Technology

Parameter variations and soft errors are the major design challenges in nanometer process technology, causing errors in the internal nodes. The basic concept for solving these problems at the circuit level, called design for variability (DFV), is to add error handling functions to the conventional circuits to increase robustness toward nanometer process-related errors. A DFV-aware finite state machine (FSM) is one of the major design challenges in nanometer circuits. Robust FSMs in a high-performance integrated circuit should not have a large area overhead, since it requires many FSMs and is usually very complex to implement. Most existing fault-tolerant FSMs can detect or correct only one bit error. We propose an area-efficient error detection and error correction architecture which can detect and correct multiple bit errors for nanometer FSMs.

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.

Analysis 2.5-D Permutation Power Transmission Line to Decrease Electro-Magnetic Influence at High Technology Nano-Fab

We present optimal permutation with 2.5-D power transmission lines system to reduce electro-magnetic influence at high technology nano-Fab. In this study, the magnetic field was lessened by mirror array power cable system, and simulation of results predicted the best permutations to decrease electromagnetic influence (EMI) value below 0.28 mG at working space without any shielding. Furthermore, this innovative method will cost down at high technology nano-Fab especially for 28 nanometer process.

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n 2) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

Physical Design Methodology for Godson-2G Microprocessor

The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core (called GS464), a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation (ICD-FP), adapted boundary constraints design optimization (ABC-OPT), automatic register group clock tree generation methodology (ARG-CTS).

Routing for manufacturability and reliability

As IC process geometries scale down to the nanometer territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability.

The Search for Alternative Computational Paradigms

Nanometer processes are characterized by extremes of process variations, noise, soft errors, and other nonidealities, which threaten to nullify the intrinsic benefits of scaling. The resulting robustness and energy efficiency problem cannot be addressed in a cost-effective manner solely through advances in manufacturing. Alternative models of computation are needed that thrive in the presence of statistical variations in the underlying device and circuit fabric. This article explores communications-inspired models of computation supported by innovative robust circuit and logic fabric design approaches. These models share the common feature of leveraging dense networks with information exchange and coupling among nodes to enhance robustness without compromising energy efficiency. Promising post-silicon devices such as carbon nanotubes (CNTs) offer an attractive platform on which to build such computational systems. This article identifies opportunities and challenges in designing robust and low-power SoCs in emerging nanoscale process technologies, employing radically new modes of computation.

Variability and New Design Paradigms

In the late- and post-silicon eras, variation of all nanometer processes will continue to increase significantly. The industry is gradually addressing this situation and exposing more variability information to the designer. According to the Gigascale Systems Research Center, the deterministic era will be over for most on-chip applications and alternatives must be found. The author of this sidebar looks forward to the time when the two will meet: when more revolutionary design techniques will find their way into practical designs, and when one of the computational paradigms will suddenly be needed to cope with an unexpected surge in variability or reliability in a particular design or technology.

A two-dimensional material removal model in magnetorheological finishing

Magnetorheological Finishing (MRF) is a new advanced optics and precision mould manufacturing technology. According to the sharp rheological characteristics of magnetorheological fluid in the magnetic field, and based on earlier research, the Preston equation, the Reynolds equation and its boundary conditions are revised and extended. The material removal model in two-dimensional directions is built and analysed by simulation. Especially the influence of workpiece materials is considered. Finally, the MRF experiment is carried out, and the influence rules of the immersed depth and material kinds are studied. The experimental data are compared with the material removal model result, which confirms the mathematical model validity. The model establishment and the processing experiment will provide the important theory and experimental references for deterministic Computer Numerical Control (CNC) nanometer process of complex optics parts.

Study on Nanometric Machining Process of Monocrystalline Si

A three-dimensional model of molecular dynamics (MD) was employed to study the nanometric machining process of Si. The model included the utilization of the Morse potential function and the Tersoff potential function to simulate the interatomic force between atoms. By analysis of snapshots and local radial distribution function (RDF) during the various stages of the cutting process, amorphous phase transformation of chip and machined surface are observed, but no phase transformation of bulk. Chip volume change is observed due to the amorphous phase transformation. Dislocations around the tool and elastic recovery of the machined surface do not appear. The effects of surface adsorption on machined surface state have been studied on the basis of surface energy and surfaces hardness. Surface energy decreases and hardness increases by adsorption. Oxygen atoms adsorbed are on the machined surface and subsurface region.

Molecular Dynamics Analyze on Effects of Abrasive Size and Cut Depth on the Monocrystal Silicon Grinding

Molecular dynamics (MD) simulation is carried out to analyze the effects of abrasive ngrain size and cut depth on monocrystal silicon grinding process. Tersoff potential is used to describe the interactions of diamond and silicon atoms. Based on classical Newtonian mechanics law, the motion equations of atoms are established and the trajectory of each atom in phase space is obtained with the aid of Velocity Verlet algorithm. Debye model is introduced to convert between kinetic energy and temperature of an atom. The grinding processes of by single grain with different size and different cut depth are investigated in atomic space. Through comparing shearing force and potential energy in the single grain grinding process, the effects of cut depth and grain size on the grinding process are discussed. From the results of MD simulation, it is revealed that when the cut depth increases, both the shearing force in silicon crystal and potential energy between the silicon atoms rise, deformation and dislocations in the silicon lattices increase. As a result, all theses lead to^more severe surface and subsurface damage. With the decreasing of grain size in the same cut-depth nanometric grinding processes, the shearing force in silicon crystal and potential energy between the silicon atoms become larger, deformation and dislocations in the silicon lattices increase.

Memory Defect Tolerance Architectures for Nanotechnologies

Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing in future submicron technologies, more advanced solutions may be required for memories to be produced in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels of several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents several Built-In Self Repair techniques addressing memories affected by high defect densities as well as an evaluation of the area cost and yield. Statistical fault injection simulations were conducted and the obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era

We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P 3 ) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P 3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.

Reliable and efficient system-on-chip design

To increase processor performance, the microprocessor industry is scaling feature sizes into the deep submicron and sub-100-nanometer regime. The recent emergence of noise and the dramatic increase in process variations have raised serious questions about using nanometer process technologies to design reliable, low-power, high-performance computing systems. The design and electronic design automation communities must work closely with the process engineering community to address these problems. Specifically, researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels.

All-Nb thin film microbridge-type Josephson junction for submillimeter-wave detection

A copolymer of methyl methacrylate (MMA) and 3-triethoxysilylpropyl methacrylate (ESPMA) was proposed as a positive-working electron beam (EB) resist of a new type. It was found that it had 4–10 times the resistance of polymethylmethacrylate (PMMA) against CBrF 3 plasma damage. The mechanism of etching Nb in reactive-ion-etching (RIE) was deciphered. Using the new EB resist and nanometer process technology, an all-Nb thin film microbridge was fabricated. It shows the a.c. Josephson effect, i.e. the Shapiro steps upto the 11th were observed under millimeter-wave (70 GHz) radiation. In addition the coherently working performance of the series array of these thin-film microbridges were observed definitively.

Properties of all-Nb thin film microbridges fabricated by nanometer process

Abstract We have fabricated all-Nb thin film microbridges by using newly developed nanometer process. These microbridges show the high sensitivity of the radiation detection. We have investigated the properties of microbridges by changing the bridge-region parameters.