Nanometer Gate Length Research Articles

Germanium- and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis

This study evaluated nanometer gate length germanium (Ge) transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors. Nanometer-scale Ge and Si junction-less field-effect transistors (JLFETs) were treated for both NFET and PFET devices under a transient response. Consequently, the electrical and thermal self-consistent simulations revealed that hole carrier transport is more challenging at the channel region for PFET, inhibiting process shrinking. Moreover, the results show that self-heating can reach a dangerous stature, particularly when the channel region is thick. This is because the operation of the nanometer-scale Ge and Si JLFETs depends on the quantum effect, which increases the band-gap energy. The suitable channel design for Ge and Si transistors is almost similar; a heavier doping concentration is favorable for Si transistors. The study concludes that optimizing the channel region to fit the band-gap energy is the most crucial aspect for designing transistors.

Vertical nanowire array-based field effect transistors for ultimate scaling

Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in "ultimate" transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.

Pulsed-laser atom probe tomography of p-type field effect transistors on Si-on-insulator substrates

Forty-five nanometer gate length p-type field effect transistors fabricated on Si-on-insulator substrates were analyzed using three-dimensional pulsed laser atom probe tomography. An optimized sample preparation methodology involving spacer etching and a change in sample orientation to align the Si/buried-SiO2 interface with the analysis direction was developed to overcome the inherent difficulties in field evaporation of insulating materials present in the device structure. Atom probe tomography analysis of samples prepared in this cross-sectional orientation was used to observe B segregation to the gate SiO2 at 5 nm from the edge of the gate, from both the poly-Si gate doping as well as the source–drain extension ion-implantation following rapid thermal annealing at 900 °C for 16 or 32 s.

Evaluation of InAs QWFET for Low Power Logic Applications

An eighty nanometer gate length InAs quantum well field effect transistors has been fabricated and the digital characteristics were evaluated. The devices show a drain-source current of 1015 mA/mm and a peak gm of 1920 mS/mm at VDS = 0.5 V. The fT and fmax are 340 GHz and 220 GHz at VDS = 0.4 V, respectively. A low delay time (CtotalV/ION) of 0.54 ps was also achieved. These excellent results indicate the InAs devices are the great potential option for the future low-power logic applications at post-Si CMOS technology.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

High-Performance In0.52Al0.48As/In0.6Ga0.4As Power Metamorphic High Electron Mobility Transistor for Ka-Band Applications

A 70 nm In0.52Al0.48As/In0.6Ga0.4As power metamorphic high electron mobility transistor (MHEMT) with a double δ-doping structure was fabricated and evaluated. The device has a high transconductance of 827 mS/mm. The saturated drain-source current of the device is 890 mA/mm. A current gain cutoff frequency ( fT) of 200 GHz and a maximum oscillation frequency ( fmax) of 300 GHz were achieved owing to the nanometer gate length and high indium content in the channel. When measured at 32 GHz, the 0.07×160 µm2 device demonstrates a maximum output power of 14.5 dBm (176 mW/mm) and a P1 dB of 11.1 dBm (80 mW/mm) with a 9.5 dB power gain. The excellent DC and RF performance of the 70 nm MHEMT are comparable to those of InP-based HEMTs and show the great potential for Ka-band power applications.

Room-temperature terahertz emission from nanometer field-effect transistors

Room-temperature generation of terahertz radiation in nanometer gate length InAlAs∕InGaAs and AlGaN∕GaN high-mobility transistors is reported. A well-defined source-drain voltage threshold for the emission exists, which depends on the gate bias. Spectral analysis of the emitted radiation is presented. The highest emission power emitted from a single device reached 0.1μW.

CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

Terahertz Detection Related to Plasma Excitations in Nanometer Gate Length Field Effect Transistor.

ABSTRACTThe channel of nanometre field effect transistor can act as a resonant cavity for plasma waves. The frequency of these plasma waves is in the Terahertz range and can be tuned by the gate length and the gate bias. During the last few years Terahertz detection and emission related to plasma wave instabilities in nanometre size field effect transistors was demonstrated experimentally. In this work we review the recent results on sub-THz and THz detection by 50-300nm gate length III-V HEMTs and Si MOSFETs. We present experimental results on the resonant and nonresonant (overdamped) plasma wave detection and discuss possible applications of nanometre field effect transistors as new detectors of THz radiations.

TeraHertz detectors based on plasma oscillations in nanometric Silicon Field Effect Transistors

We report on the experiments about detection of the THz radiation by silicon FETs with nanometer gate lengths. The observed photo-responses measured as a function of the gate voltage are all in agreement with the predictions of the Dyakonov-Shur theory. The plasma wave parameters deduced from the experiments allow us to predict also the possibility of resonant detection in THz range by nanometer size silicon devices. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Plasma wave detection of sub-terahertz and terahertz radiation by silicon field-effect transistors

We report on experiments on photoresponse to sub-THz (120GHz) radiation of Si field-effect transistors (FETs) with nanometer and submicron gate lengths at 300K. The observed photoresponse is in agreement with predictions of the Dyakonov–Shur plasma wave detection theory. This is experimental evidence of the plasma wave detection by silicon FETs. The plasma wave parameters deduced from the experiments allow us to predict the nonresonant and resonant detection in THz range by nanometer size silicon devices—operating at room temperature.

Comparative study of self-aligned and nonself-aligned SiGe p-metal–oxide–semiconductor modulation-doped field effect transistors with nanometer gate lengths

A self-aligned process used to fabricate p-type SiGe metal–oxide–semiconductor modulation-doped field effect transistors (MOS-MODFET) is described. Self- and nonself-aligned p-type Si0.2Ge0.8/Si0.7Ge0.3 MOS-MODFETs with gate-lengths from 1 μm down to 100 nm were fabricated. The dc and microwave characteristics of these devices are presented. In comparison with nonself-aligned devices, self-aligned devices exhibited higher extrinsic transconductances, lower threshold voltages, higher unity current gain cutoff frequencies fT, and maximum oscillation frequencies fMAX. Self-aligned MOS-MODFETs with a gate length of 100 nm exhibited an extrinsic transconductance of 320 mS/mm, an fT of 64 GHz, and an fMAX of 77 GHz. To our knowledge, these are the highest data ever reported for any MOS-type p-FETs with a SiGe channel. All these excellent performances were measured at very low drain and gate biases.