Nano-floating Gate Memory Research Articles

Organic Electronics: Printed, Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics (Adv. Funct. Mater. 28/2013)

High-performance, top-gated, organic, nanofloating gate memory (NFGM) devices fabricated using spatially well-distributed metallic nanoparticles as a floating gate and dielectrics with long charge relaxation properties are reported by Kang-Jun Baeg, Yong-Young Noh, Dong-Yu Kim, and co-workers on page 3503. The organic NFGM devices show wide memory windows, a high on/off current ratio, and quasi-permanent retention characteristics. The 256-bit NFGM array is also fabricated successfully on a flexible polyethylene naphthalate (PEN) substrate.

Printed, Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

AbstractThe effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm2 V−1 s−1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (Ion/Ioff ≈ 105), and a long extrapolated retention time (>107 s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high Ion/Ioff (≈104 ± 0.85), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.

Design of control oxide thickness for multi-level storage in a stepped NFGM MOSCAP

In this work, the effect of control oxide thickness on the storage characteristic of MOSCAP based on nano floating gate memory (NFGM) structure was explored in order to apply the results to a stepped NFGM. A stepped MOSCAP structure can realize multi-level storage characteristic via control of electric field strength in the tunneling oxide using a stepped control oxide. Through simulation, we have predicted that a 20 nm step height is optimal to exhibit multi-level storage behavior for a 40 nm thick HfO2 control oxide. First, we prepared two step-free NFGM MOSCAP structures consisting of Au nanocrystals: one with 20 nm thick HfO2 control oxide and the other with 40 nm thick HfO2 control oxide. The C–V behavior of NFGM MOSCAP structures having different control oxide thicknesses was measured in a parallel mode in order to simulate the stepped MOSCAP structure. Finally a stepped NFGM MOSCAP stricture was fabricated. As a consequence, we successfully demonstrated multi-level storage behavior in an NFGM MOSCAP structure with 40/20 nm step-shape control oxide as simulation predicted.

Non-volatile nano-floating gate memory with Pt-Fe2O3 composite nanoparticles and indium gallium zinc oxide channel

Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe2O3 composite nanoparticles with a mostly core–shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe2O3 nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles’ layer could be formed with a density of ~3 × 1011 cm−2 by a solution-based dip-coating process. The Pt core (~3 nm in diameter) and Fe2O3-shell (~6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current–voltage measurement with a threshold voltage shift of ~4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of ~0.66 V after pulse programming at +20 V for 1 s with retention > ~65 % after 104 s. These results demonstrate the feasibility of using colloidal nanoparticles with core–shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

Flexible Nano-Floating-Gate Memory With Channels of Enhancement-Mode Si Nanowires

The electrical characteristics of a flexible nano-floating-gate memory (NFGM) device with a channel made of an enhancement-mode n+-p-n+ Si nanowire (Si-NW) are investigated in this work. The NFGM based on the enhancement-mode Si-NW field-effect transistor is constructed on a plastic substrate with a Pt-nanocrystal floating-gate layer; it exhibits an on-current/off-current ratio of ~107 and a subthreshold swing of 88 mV/dec. The NFGM shows good memory characteristics and mechanical flexibility, such as a threshold voltage shift of 1.85 V, a retention time of up to ~104s, and a stability for up to 1000 bending cycles. The present study demonstrates the promising potential of flexible Si-NW-based nonvolatile memories for future electronics.

Fabrication of Arrayed Si Nanowire-Based Nano-Floating Gate Memory Devices on Flexible Plastics

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Improving the characteristics of an organic nano floating gate memory by a self-assembled monolayer

We demonstrate a novel approach to improve the characteristics of the gold nanoparticle-based organic transistor memory devices by using self-assembled monolayers (SAM) with different functional groups as interfacial modifier. SAM-based interfacial engineering significantly improved the hysteresis, memory window, and on/off ratio of a nano floating gate memory (NFGM) at zero gate voltage. This NFGM showed a large memory window of up to 190 V and on/off current ratio of 10(5) during writing and erasing with an operation voltage of 100 V of gate bias in a short time, less than 1 s. Furthermore, the devices show excellent nonvolatile behavior for bistable switching. The ON and OFF state can be stably maintained for 10(3) s with an I(on)/I(off) current ratio of 10(6) for a pentafluorophenyl trimethoxysilane modified device. The results suggested the importance of SAM-modified interface for the memory performance of NFGMs.

Reduced Distribution of Threshold Voltage Shift in Double Layer NiSi2 Nanocrystals for Nano-Floating Gate Memory Applications

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Formation of Cu or Cu2O Nanoparticles Embedded in a Polyimide Film for Nanofloating Gate Memory

Cu and Cu2O nanoparticles were fabricated in polyimide by curing the stacked polyamic acid/Cu/polyamic acid on Si wafer and post heat treatment. Nanoparticle distribution in polyimide (a monolayer of vertically aligned nanoparticles or the randomly dispersed nanoparticles) can be controlled by changing the reactivity of Cu with PAA and curing atmosphere. About 6-7 nm sized Cu or Cu2O nanoparticles were observed in the polyimide film. The capacitance-voltage curves were measured with Al/particles in polyimide/p-Si(100) specimens at 300 K, and the capacitance hystereses were observed at different sweep voltage ranges, which indicates that Cu2O or Cu nanoparticles can be utilized in next generation flash memories.

Review paper: Nano-floating gate memory devices

In recent decades, memory device technology has advanced through active research and the development of innovative technologies. Single transistor-based flash memory device is one of the most widely used forms of memory devices because their device structure is simple and the scaling is feasible. A nano-floating gate memory (NFGM) device is a kind of flash memory devices that uses nanocrystals as a charge-trapping element. The use of nanocrystals has advantages over memory devices that rely on other methods such as discontinuous trap sites and controllable trap levels. Nowadays considerable progress has been made in the field of NFGM devices, and novel application areas have been explored extensively. This review article focuses on new technologies that are advancing these developments. The discussion highlights recent efforts and research activities regarding the fabrication and characterization of nonvolatile memory devices that use a nanocrystal layer as a charge-trapping element. The review concludes with an analysis of device fabrication strategies and device architectures of NFGM devices for possible application to devices that are organic, printed, and flexible.

High-performance and room-temperature-processed nanofloating gate memory devices based on top-gate transparent thin-film transistors

Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.

ZnO 나노선 트랜지스터를 기반으로 하는 Al 나노입자플로팅 게이트 메모리 소자의 특성

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

Retention Characteristics of Schottky Barrier Tunneling Transistor-Nano Floating Gate Memory with Various Side Walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.

Nanofloating Gate Memory Devices Based on Controlled Metallic Nanoparticle-Embedded InGaZnO TFTs

In this letter, InGaZnO thin-film transistor (bottom-gate (n <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> Si) and top-contact structure)-based nanofloating gate memory devices were developed. These nonvolatile transistor memory devices contained self-assembled gold nanoparticles ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \hbox{Au}_{\rm NP}$</tex></formula> ) and exhibited good programmable memory characteristics according to the programming/erasing operations with large memory windows. The charge trapping in the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge storage layers was responsible for the memory operations. The good endurance and data retention capability demonstrated by these memory devices make them suitable for nonvolatile memory applications. As this approach was based on the solution-processed controlled <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge trapping layers and the low-temperature synthesized transparent oxide semiconductors, it has the potential for application in low-temperature-processed transparent nonvolatile memory devices.

Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics.

Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm2/V·s and their on/off ratio was in the range of 104–105. The threshold voltages of the programmed and erased states were negligibly changed up to 103 cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics.

Nano-floating gate memory based on ZnO thin-film transistors and Al nanoparticles

In this study, nonvolatile nano-floating gate memory devices were fabricated based on ZnO films and Al nanoparticles and their electrical properties were investigated. Al nanoparticles were embedded in between SiO 2 tunneling and control oxide layers deposited on ZnO channels, and these nanoparticles acted as floating gate nodes in the devices. Their electron mobility, on/off ratio, and threshold voltage shift were estimated to be 9.42 cm 2/V s, about 10 6, and 4.2 V, respectively. Their programming/erasing, endurance and retention were also characterized. Especially, the low-temperature processes applied in this work indicate that integrated electronic devices can be fabricated on temperature-sensitive substrates.

Transparent nano-floating gate memory on glass

We construct fully transparent nano-floating gate memory devices on a glass substrate.These memory thin-film transistors consist of channel layers of ZnO films, electrodes ofAl/ITO, and floating gate nodes of Al nanoparticles, exhibiting a transmittance of ∼ 71% in the visible region. Their electron mobility,on/off ratio, and threshold voltage shift are estimated to be0.92 cm2 V − 1 s − 1, about104, and 3.1 V, respectively. Moreover, their programming/erasing, endurance and retention arecharacterized in this study. Our study suggests that our memory devices have greatpotential for realizing transparent systems-on-glass.

Characteristics of a Multiple Alloy Nanodot Memory with an Enhanced Charge Storage Capability

A nano-floating gate memory structure with a controllable large threshold voltage window using the Fowler–Nordheim (FN) tunneling program and erasing is proposed. This structure has multiple dot layers composed of a uniform single alloy dot layer in the surrounding silicon dioxide layer and a uniform interoxide layer between these dot layers. Here, we confirmed that multiple alloy FePt nanodot layers provide more charge storage than a single layer, which gives a larger memory window. Thus, multiple nanodot layers can store more charges corresponding to the number of layers with the optimization of several parameters, such as blocking oxide layer thickness. In addition, high operation voltages, low operation speeds due to a thick blocking oxide layer, and the poor retention related to the device structure were revealed, and the improvement of this issue was also discussed. Despite several issues, it is expected that a multiple FePt nanodot memory using FN tunneling will be a candidate structure for a future flash memory because of its larger memory window.

High-performance organic charge trap flash memory devices based on ink-jet printed 6,13-bis(triisopropylsilylethynyl) pentacene transistors

Organic nanofloating gate memory devices were developed based on ink-jet printed 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene thin-film transistors (TFTs) embedding gold nanoparticles. The programming/erasing operations showed that the organic memory devices exhibited good programmable memory characteristics that resulted in a gate-voltage controlled reliable threshold voltage shift of the programmed/erased states. The data retention and endurance measurements also showed the reliable nonvolatile memory properties. Solution processes were used for synthesis of the charge trapping elements and TIPS-pentacene TFTs were made by the ink-jet printing technique at low temperatures. Therefore, these processes can readily be adopted in all-printed organic memory devices on flexible substrates.

P-type silicon nanowire-based nano-floating gate memory with Au nanoparticles embedded in Al 2O 3 gate layers

P-type Si nanowire (NW)-based nano-floating gate memory (NFGM) with Au nanoparticles (NPs) embedded in Al 2O 3 gate layers is characterized in this study. The electrical characteristics of a representative p-type Si NW-based NFGM exhibit a counterclockwise hysteresis loop indicating the trapping and detrapping of electrons in the Au NP nodes of the NFGM device. The threshold voltage shift of the device is 5.4 V and the device has good retention over a lapse of time of 5 × 10 4 s. On the other hand, the p-type Si NW-based top-gate device without any Au NPs does not exhibit any significant threshold voltage shift. This observation reveals that the memory behavior of the p-type Si NW-based NFGM is due to the trapping and detrapping of charge carriers in the Au NPs.