Nano-floating Gate Memory Devices Research Articles

2D superlattices via interfacial self-assembly of polymer-grafted Au nanoparticles.

Nanoparticle (NP) superlattices are periodic arrays of nanoscale building blocks. Because of the collective effect between functional NPs, NP superlattices can exhibit exciting new properties that are distinct from those of individual NPs or corresponding bulk materials. In particular, two-dimensional (2D) NP superlattices have attracted increasing attention due to their emerging applications in micro/opto-electronics, catalysis, sensing, and other fields. Among various preparation methods, evaporation-induced interfacial self-assembly has become the most popular method for preparing 2D NP superlattices because it is a simple, low-cost, and scalable process that can be widely applied to various NPs. Introducing soft ligands, such as polymers, can not only provide convenience in controlling the self-assembly process and tuning superlattice structures but also improve the properties of 2D NP superlattices. This feature article focuses on the methods of evaporation-induced self-assembly of polymer-grafted Au NPs into free-standing 2D NP superlattice films at air/liquid interfaces and 2D NP superlattice coatings on substrates, followed by studies on in situ tracking of the self-assembly evolution process through small-angle X-ray scattering. Their application in nano-floating gate memory devices is also included. Finally, the challenges and perspectives of this direction are discussed.

Hydrophobic cross-linked nanoparticles comprising polystyrene and poly(thiophene-diketopyrrolopyrrole) segments for non-volatile memory applications

Molecular nano-floating gate memory devices using triblock conjugated polymer nanoparticles are a promising strategy for high-performance nonvolatile memory and artificial synapses.

Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate

Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.

Well-ordered nanoparticle arrays for floating gate memory applications

A non-volatile floating gate memory device containing well-ordered Au nanoparticles (NPs) is fabricated as a metal–oxide–semiconductor capacitor structure. With superior control on the size, shape and position of nanoparticles, the presented nano-floating gate memory (NFGM) device possesses almost perfect precision of device geometry. The well-ordered Au NPs embedded within the memory device exhibit large memory window at low operation voltages (8.8V @ ± 15V), fast operation time (<10−4 s) and good retention (up to 107 s). In this work, the structural properties of the NFGM device are correlated with the examined electrical properties. The current results are compared with the other studies in the literature to emphasis the advantages of the precise ordering and geometry of the NPs.

A Centimeter-Scale Inorganic Nanoparticle Superlattice Monolayer with Non-Close-Packing and its High Performance in Memory Devices.

Due to the near-field coupling effect, non-close-packed nanoparticle (NP) assemblies with tunable interparticle distance (d) attract great attention and show huge potential applications in various functional devices, e.g., organic nano-floating-gate memory (NFGM) devices. Unfortunately, the fabrication of device-scale non-close-packed 2D NPs material still remains a challenge, limiting its practical applications. Here, a facile yet robust "rapid liquid-liquid interface assembly" strategy is reported to generate a non-close-packed AuNP superlattice monolayer (SM) on a centimeter scale for high-performance pentacene-based NFGM. The d and hence the surface plasmon resonance spectra of SM can be tailored by adjusting the molecular weight of tethered polymers. Precise control over the d value allows the successful fabrication of photosensitive NFGM devices with highly tunable performances from short-term memory to nonvolatile data storage. The best performing nonvolatile memory device shows remarkable 8-level (3-bit) storage and a memory ratio over 105 even after 10 years compared with traditional devices with a AuNP amorphous monolayer. This work provides a new opportunity to obtain large area 2D NPs materials with non-close-packed structure, which is significantly meaningful to microelectronic, photovoltaics devices, and biochemical sensors.

N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate

In this paper, n type nonvolatile memory devices were fabricated by implanting a bilayer (rGO sheets/Au NP) floating gates, using n-type polymer semiconductor, poly {[N, N′ bis (2octyldodecyl) - naphthalene-1, 4, 5, 8 - bis (dicarboximide)-2,6-diyl] – alt - 5,5′ - (2, 2′ bithiophene)} [P(NDI2OD-T2)n]. In the developed organic field effect transistor memory devices, electrons are trapped/detrapped in rGO sheet/Au NP's nano-floating gates by controlling the charge carrier density in the active layer through back gate bias control. The devices showed interesting non-volatile memory properties with a large memory window of ∼34 V, a programming-reading-erasing cycling endurance of 103 times and most importantly, an improved retention time characteristics estimated by extrapolation (longer than the technological requirement of commercial memory devices (>10 years)). This approach provides a great potential for fabricating high-performances organic nano-floating gate memory devices and opens up a new way for the development of next-generation non-volatile memory devices.

Graphene quantum dots as a highly efficient solution-processed charge trapping medium for organic nano-floating gate memory

A highly efficient solution-processible charge trapping medium is a prerequisite to developing high-performance organic nano-floating gate memory (NFGM) devices. Although several candidates for the charge trapping layer have been proposed for organic memory, a method for significantly increasing the density of stored charges in nanoscale layers remains a considerable challenge. Here, solution-processible graphene quantum dots (GQDs) were prepared by a modified thermal plasma jet method; the GQDs were mostly composed of carbon without any serious oxidation, which was confirmed by x-ray photoelectron spectroscopy. These GQDs have multiple energy levels because of their size distribution, and they can be effectively utilized as charge trapping media for organic NFGM applications. The NFGM device exhibited excellent reversible switching characteristics, with an on/off current ratio greater than 106, a stable retention time of 104 s and reliable cycling endurance over 100 cycles. In particular, we estimated that the GQDs layer trapped ∼7.2 × 1012 cm−2 charges per unit area, which is a much higher density than those of other solution-processible nanomaterials, suggesting that the GQDs layer holds promise as a highly efficient nanoscale charge trapping material.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices.

Vertical stacking of ZnO nanowire devices with different functionalities on plastic substrates

In this paper, we demonstrate the vertical stacking of ZnO nanowire (NW) field-effect transistors (FETs), a ZnO NW-based nanofloating gate memory (NFGM) device, and a ZnO NW-based inverter on a flexible plastic substrate. For the vertical stacking, four ZnO NW devices are sequentially constructed on each of four layers, and these devices are isolated from each other using Al2O3 material. Each of the stacked ZnO NW devices exhibits the good electrical characteristics with n-type depletion modes under both the flat and bent states. Moreover, the switching, memory, and inverting characteristics of the stacked ZnO NW devices are examined.

High-performance organic nano-floating-gate memory devices based on graphite nanocrystals as charge-trapping elements and high-k Ta2O5 as a controlled gate dielectric

A new type of high-performance organic nano-floating-gate memory (NFGM) device has been fabricated by integrating graphite nanocrystals (GNCs) as charge-trapping elements and high-k Ta2O5 as a controlled gate dielectric. The GNC nano-floating-gates have a high density of charge trapping sites, and they are electrically separated enabling the reduction of stored charge leakage. With a relatively low-voltage programming pulse (−2 V, 1 μs), the fabricated devices exhibit a significant negative threshold voltage shift of 1.3 V, and programming/erasing switching times of less than 10 ns are observed. Furthermore, the NFGM devices show a long retention time of more than 10 years at room temperature along with robust endurance properties with 104 cycles of repeated programming/erasing. This approach provides an outstanding alternative approach for fabricating high-performance GNC-based organic NFGM devices and opens up a new route for the development of next-generation non-volatile memory devices.

All-solution-processed nonvolatile flexible nano-floating gate memory devices

Organic semiconductors have great potential for future electronic applications owing to their inherent flexibility, low cost, light weight and ability to easily cover large areas. However, all of these advantageous material properties can only be harnessed if simple, cheap and low-temperature fabrication processes, which exclude the need for vacuum deposition and are compatible with flexible plastic substrates, are employed. There are a few solution-based techniques such as spin-coating and inkjet printing that meet the above criteria. In this paper, we describe a novel all-solution-processed nonvolatile memory device fabricated on a flexible plastic substrate. The source, drain and gate electrodes were printed using an inkjet printer with a conducting organic solution, while the semiconducting layer was spin-coated with an n-type polymer. The charge-trapping layer was composed of spin-coated reduced graphene oxide (rGO), which was prepared in the form of a solution using Hummer’s method. The fabricated device was characterized in order to confirm the memory characteristics. Device parameters such as threshold voltage shift, retention/endurance characteristics, mechanical robustness and reliability upon bending were also analyzed.

Memory Characteristics of Doubly Stacked Nano-Floating Gate Memory Devices with Channels of Single ZnO Nanowires

We present in this paper the memory characteristics of doubly stacked nonvolatile nano-floating gate memory (NFGM) devices with channels of single ZnO nanowires. In our doubly stacked NFGM devices, first- and second-stage floating gate layers composed of Al nanoparticles (NPs) are separated with a 3-nm-thick interlayer of Al2O3. The average size of Al NPs created by sputtering is about 7 nm, and the Al NPs are isolated from each other laterally in the same layer as well as vertically in the double layers. When the voltage is swept from 10 to -10 V, the flat-band voltage shifts are about 0.8 and 2.5 V for the singly and doubly stacked MOS capacitors, respectively. The comparison of metal-oxide-semiconductor capacitors embedded with singly and doubly stacked nanoparticle layers reveals that the retention characteristics of the doubly stacked NFGM device are superior to those of a singly stacked NFGM device. Furthermore, the memory characteristics of the doubly stacked NFGM device remain even after 10(5) programming and erasing cycles.

Organic Electronics: Printed, Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics (Adv. Funct. Mater. 28/2013)

High-performance, top-gated, organic, nanofloating gate memory (NFGM) devices fabricated using spatially well-distributed metallic nanoparticles as a floating gate and dielectrics with long charge relaxation properties are reported by Kang-Jun Baeg, Yong-Young Noh, Dong-Yu Kim, and co-workers on page 3503. The organic NFGM devices show wide memory windows, a high on/off current ratio, and quasi-permanent retention characteristics. The 256-bit NFGM array is also fabricated successfully on a flexible polyethylene naphthalate (PEN) substrate.

Printed, Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

AbstractThe effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm2 V−1 s−1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (Ion/Ioff ≈ 105), and a long extrapolated retention time (&gt;107 s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high Ion/Ioff (≈104 ± 0.85), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.

Fabrication of Arrayed Si Nanowire-Based Nano-Floating Gate Memory Devices on Flexible Plastics

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Review paper: Nano-floating gate memory devices

In recent decades, memory device technology has advanced through active research and the development of innovative technologies. Single transistor-based flash memory device is one of the most widely used forms of memory devices because their device structure is simple and the scaling is feasible. A nano-floating gate memory (NFGM) device is a kind of flash memory devices that uses nanocrystals as a charge-trapping element. The use of nanocrystals has advantages over memory devices that rely on other methods such as discontinuous trap sites and controllable trap levels. Nowadays considerable progress has been made in the field of NFGM devices, and novel application areas have been explored extensively. This review article focuses on new technologies that are advancing these developments. The discussion highlights recent efforts and research activities regarding the fabrication and characterization of nonvolatile memory devices that use a nanocrystal layer as a charge-trapping element. The review concludes with an analysis of device fabrication strategies and device architectures of NFGM devices for possible application to devices that are organic, printed, and flexible.

High-performance and room-temperature-processed nanofloating gate memory devices based on top-gate transparent thin-film transistors

Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.

ZnO 나노선 트랜지스터를 기반으로 하는 Al 나노입자플로팅 게이트 메모리 소자의 특성

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

Retention Characteristics of Schottky Barrier Tunneling Transistor-Nano Floating Gate Memory with Various Side Walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.

Nanofloating Gate Memory Devices Based on Controlled Metallic Nanoparticle-Embedded InGaZnO TFTs

In this letter, InGaZnO thin-film transistor (bottom-gate (n <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> Si) and top-contact structure)-based nanofloating gate memory devices were developed. These nonvolatile transistor memory devices contained self-assembled gold nanoparticles ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \hbox{Au}_{\rm NP}$</tex></formula> ) and exhibited good programmable memory characteristics according to the programming/erasing operations with large memory windows. The charge trapping in the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge storage layers was responsible for the memory operations. The good endurance and data retention capability demonstrated by these memory devices make them suitable for nonvolatile memory applications. As this approach was based on the solution-processed controlled <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge trapping layers and the low-temperature synthesized transparent oxide semiconductors, it has the potential for application in low-temperature-processed transparent nonvolatile memory devices.