NAND Gates Research Articles

Actively switchable terahertz Spiral-Shaped metamaterial with programmable performance

Two designs of actively switchable terahertz (THz) spiral-shaped metamaterial (SSM) are presented in this study. They are composed of four spiral meta-atoms with different orientations. The electromagnetic responses of SSM devices show the fifth-resonance to provide five switching windows for binary encoding due to their transmission intensities with polarization-dependent characteristic. In addition, by actively changing the configuration of elevated spiral meta-atoms, a dual-resonance switching function can be realized. It proves the binary encoding and logic operation such as NAND and OR gates. These characteristics indicate that the proposed SSM designs can be promising optoelectronic switching and multi-bit programmable devices in the THz spectrum.

New partitioned domino circuit for power-efficient wide gates

In this article, a new domino circuit is presented to decrease the power consumption of wide gates without considerable performance and robustness degradation. The suggested circuit technique modifies the output inverter to decrease the switching power by decreasing the voltage swing. Moreover, the wide pull-down networks can be partitioned into smaller networks. To merge the partitioned pull-down networks, a dynamic NAND gate is employed to increase the circuit performance. Using the proposed technique, the leakage current is decreased in the wide gates because of the stacking effect. Also, the noise immunity is improved due to the body effect. The wide OR gates are simulated in 90-nm CMOS technology. Simulation results show 54% power reduction and 2.55 times improvement in the noise immunity at the same speed in comparison with the conventional circuit technique for 64-input OR gates. In addition, a 128-input AND-OR gate is designed using the proposed circuit. Results demonstrate that power and delay are reduced by 39% and 11%, respectively, compared to the conventional AND-OR gate at the same robustness.

Plasmonic Logic Gates at Optimum Optical Communications Wavelength

This paper displays a design that realizes all optical logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and consisting of one nanoring and four strips Operates on the principle of resonance. the proposed design works at the wavelength of 1550 nm using insulator-metal-insulator (IMI) plasmonic waveguide. The basic principle of the operation of these gates is input and control signals’ constructive and destructive interference. The proposed transmission threshold’s value is 0.25 between OFF state and ON state. The proposed design has small dimensions (300 nm × 300 nm) and can realize seven logic gates with maximum transmission 134% at NOT gate, 223% at OR gate, 134% at NAND gate and 223% at XNOR gate where the design is optimum and excellent design and the modulation depth is very high because it’s ranges in all gates more than 90%. The proposed structure contributes in building nanocircuits for integrated photonic circuits and optical signal processing.

Skyrmion-based logic gates controlled by electric currents in synthetic antiferromagnet

Skyrmions in synthetic antiferromagnetic (SAF) systems have attracted much attention in recent years due to their superior stability, high-speed mobility, and completely compensated skyrmion Hall effect. They are promising building blocks for the next generation of magnetic storage and computing devices with ultra-low energy and ultra-high density. Here, we theoretically investigate the motion of a skyrmion in an SAF bilayer racetrack and find the velocity of a skyrmion can be controlled jointly by the edge effect and the driving force induced by the spin current. Furthermore, we propose a logic gate that can realize different logic functions of logic AND, OR, NOT, NAND, NOR, and XOR gates. Several effects including the spin–orbit torque, the skyrmion Hall effect, skyrmion–skyrmion repulsion, and skyrmion–edge interaction are considered in this design. Our work may provide a way to utilize the SAF skyrmion as a versatile information carrier for future energy-efficient logic gates.

Logic Locking of Integrated Circuits Enabled by Nanoscale MoS2-Based Memtransistors

With an ever-increasing globalization of the semiconductor chip manufacturing supply chain coupled with soaring complexity of modern-day integrated circuits (ICs), intellectual property (IP) piracy, reverse engineering, counterfeiting, and hardware trojan insertion have emerged as severe threats that have compromised the security of critical hardware components. Logic locking (LL) is an IP protection technique that can mitigate these threats by locking a given IC with a secret key. Earlier LL demonstrations based on traditional silicon complementary metal-oxide-semiconductor (CMOS) technology and emerging memristors require significant hardware investment in the form of additional input gates and extensive CMOS peripherals, rendering them area- and energy-inefficient. In this article, we demonstrate multiple two-dimensional (2D) nanoscale memtransistor-based programmable logic gates such as AND, NAND, OR, XOR, and NOT gates, each of which can be locked/unlocked without requiring peripherals and at minuscule energy expenditure (<1 pJ). We also show that SAT-solver is unsuccessful in breaking into any of the ISCAS’85 benchmark circuits that utilize our LL scheme. The massive resilience to SAT-attack is attributed to the prowess of programmable 2D memtransistors which enable device-level LL of all the gates in each of the benchmark circuits. Given that 2D transistors are drawing increasing attention of chip manufacturing corporations like Intel, TSMC, etc., to replace and/or augment silicon at aggressively scaled technology nodes, our demonstration of area- and energy-efficient LL can be considered as a step toward the realization of secure ICs enabled by 2D nanoscale memtransistors.

In‐Memory Computing of Multilevel Ferroelectric Domain Wall Diodes at LiNbO3 Interfaces

AbstractDirect data processing in nonvolatile memories can enable area‐ and energy‐efficient computation, unlike independent performance between separate processing and memory units; repetitive data transfer between these units represents a fundamental performance limitation in modern computers. Spatially mobile conducting domain walls in ferroelectrics can be redirected between drain, gate, and source electrodes to function as nonvolatile transistors with superior energy efficiency, ultrafast operating and communication speeds, and high logic/storage densities. Here, in‐memory computing is demonstrated using multilevel domain wall diodes at LiNbO3 interfaces. Ultrathin domains within interfacial layers between each mesa‐like memory cell and the contact electrodes can rectify diode‐like domain wall currents with on/off current ratios exceeding 107 at low operating voltages, surpassing the performance of traditional p‐n junctions using built‐in potentials across depletion layers. NOT, NAND, and NOR gate logic functions are demonstrated, providing insights into high‐density integration of multilevel storage and computational units in all‐ferroelectric domain wall devices.

Optimization of an all-optical three-input universal logic gate with an enhanced contrast ratio by exploiting a T-shaped photonic crystal waveguide.

Universal gates (NAND and NOR) are used for any electronic circuit that is affordable and straightforward to build all logic gates (LoG). In this work, the T-shaped 2D photonic crystal (PhC) is exploited to design a three-input universal LoG premised on the beam-interference principle. The design criteria of pitch (a), rod radius (r), and refractive index (n) are employed to obtain a high impact output. The methodologies of plane wave expansion and finite-difference time-domain are employed for examining the framework of universal LoG at 1550 nm wavelengths (λ). The suggested universal LoG design has a compact size of 8.4µm×4.8µm. Additionally, the structure yields a high contrast ratio (CR) of 20.37 dB for the NAND LoG and 28.45 dB for the NOR LoG, and maximum transmission efficiency of 50.6% and 70% for the NAND and NOR gates; correspondingly, the best and worst three-input NAND gate response times are 19.5 ps and 21.4 ps. Similarly, the response time of the three-input NOR gate is 26 ps. The proposed universal gate's primary goal is to offer a high CR and a compact structure while being compatible with any other logic gate.

Ultralow-Thermal-Budget-Driven IWO-Based Thin-Film Transistors and Application Explorations.

Exploiting multifunctional thin film transistors (TFTs) by low-temperature manufacturing strategy is a crucial step toward flexible electronics. Herein, a multifunctional indium–tungsten-oxide (IWO)-based TFT, gated by solid-state chitosan electrolyte membrane, is fabricated on paper substrate at room temperature. The chitosan exhibits a high specific electric-double-layer capacitance of 2.0 µF cm−2 due to the existence of mobile protons. The IWO-based TFT possesses excellent electrical properties, including a low threshold voltage of 0.2 V, larger current switching ratio of 1.3 × 106, high field effect mobility of 15.0 cm2 V−1s−1, and small subthreshold swing of 117 mV/decade, respectively. Multifunctional operations including inverter, Schmitt triggers, and NAND gate are successfully demonstrated. As an example of information processing, the essential signal transmission functions of biological synapses also be emulated in the fabricated IWO-based TFTs. The experimental results indicate that such flexible IWO-based TFTs on low-cost and biodegradable paper provide the new-concept building blocks for flexible electronics.

All-Polymer Bulk-Heterojunction Organic Electrochemical Transistors with Balanced Ionic and Electronic Transport.

The rapid development of organic electrochemical transistor (OECTs)-based circuits brings new opportunities for next-generation integrated bioelectronics. The all-polymer bulk-heterojunction (BHJ) offers an attractive, inexpensive alternative to achieve efficient ambipolar OECTs, and building blocks of logic circuits constructed from them, but have not been investigated to date. Here, the first all-polymer BHJ-based OECTs are reported, consisting of a blend of new p-type ladder conjugated polymer and a state-of-the-art n-type ladder polymer. The whole ladder-type polymer BHJ also proves that side chains are not necessary for good ion transport. Instead, the polymer nanostructures play a critical role in the ion penetration and transportation and thus in the device performance. It also provides a facile strategy and simplifies the fabrication process, forgoing the need to pattern multiple active layers. In addition, the development of complementary metal-oxide-semiconductor (CMOS)-like OECTs allows the pursuit of advanced functional logic circuitry, including inverters and NAND gates, as well as for amplifying electrophysiology signals. This work opens a new approach to the design of new materials for OECTs and will contribute to the development of organic heterojunctions for ambipolar OECTs toward high-performing logic circuits.

Performance Evaluation of a Low Energy Universal Gate for VLSI with 16nm Technology

NAND &amp; NOR logic gates are general purpose logic gates that can be used to build other logic gates. This article describes a new NAND gate based on 3T (3 transistors) which has the correct output logic level and behaves similarly to the previous design NAND gate logic. The proposed structure has faster processing and lower power consumptionwhat makes it ideal for large-scale integration (VLSI) applications. Typical 16nm CMOS fabrication techniques were used for simulation, building Nand Gate, and to compare it to Nand Gate with different techniques and design such as using four transistors. It turns out that the amount of delay in this desgin with the selected technology compared to other projects with other technologies is less, that is, 0.02966 ns, which proves that the smaller the delay, the faster the gate operates.

Cylindrical Indentation to Selectively Stress Nanoscale CMOS Transistors

Advanced indentation techniques have been introduced to study the effects of multiple stresses on the transistor characteristics with using a cylindrical tip with various alignments. Particularly, controlling the cylinder tip orientation relative to the transistor channel direction is proposed to selectively strain the silicon channels in order to induce very different selectively controlled stresses. Several tip alignments allow to shift the stresses from uniaxial towards biaxial stress as well as to induce shear stress. Ring oscillator circuits based on NAND and NOR gates are used to monitor the stress effects on the characteristic circuit frequency as well as on the individual transistors. Finite Element simulations help to identify optimized setup properties for the targeted application. Comparison with previous indentation experiments derives the specific influence of each stress tensor component on the transistor characteristics.

Acoustic computing: At tunable pseudospin-1 Hermitian Dirac-like cone.

Hermitian Dirac-like cones are proposed for creating acoustic logic gates herein. The predictive phenomenon of creating Dirac-like cones near a bipolar antisymmetric deaf band was found to be useful for acoustic computing of Boolean algebra. Unlike previous approaches, Dirac-like cone creates exclusive opportunity to perform all possible Boolean algebra computation with valid inputs. The phenomenon is demonstrated in two-dimensional phononic crystals (PnCs), consisting of tunable square columns in air media. By predictive tuning of the deaf bands, a triply to doubly degenerated Dirac-like cone is reported to form and is particularly useful for acoustic computing. It is only possible when a bottom band has a negative curvature that is lifted from a nearby doubly degenerated band with positive curvature, which is again degenerated with a deaf band. On the contrary, similar computing possibilities are difficult when the bottom band degenerates with the deaf band and the top band is lifted. Using these phenomena, acoustic logic gates are designed to perform Boolean algebra through AND, NAND, OR, and NOR gate operations. A simple one degree of freedom system and a complex six degrees of freedom system are proposed and demonstrated in which simple rotation of the PnCs activates a specific gate.

Screen printing of graphene-based nanocomposite inks for flexible organic integrated circuits

Graphene and multiwalled carbon nanotube (CNT) composites have been reported to be suitable conductive inks for screen-printing technology, which is a viable option for electrode patterning in organic integrated circuits. Considering the physical properties of the graphene–CNT composite ink, the optimized screen-printing conditions produce graphene–CNT patterns with good pattern fidelity. In addition, the use of a centrifugal mixer enables the composite to disperse graphene and CNT molecules well, stabilizing electrical conductance. In this study, these screen-printed graphene–CNT electrodes were applied to fabricate organic field-effect transistors (OFETs) on a glass substrate. The p- and n-type devices performed satisfactorily. Furthermore, screen printing of graphene–CNT enabled the integration of OFETs for fabricating complementary inverters, NAND, and NOR gates. We believe that the characterization of graphene–CNT inks can promote the advancement of organic integrated circuits beyond unit OFET devices based on an easy-to-use screen-printing technique. • Graphene/CNT composite ink was developed for screen-printing technique. • Using a centrifugal mixer produced well-distributed graphene/CNT patterns with high fidelity. • Integrated circuits with screen-printed graphene/CNT showed robust operation.

Reconfigurable electro-optical logic gates using a 2-layer multilayer perceptron

In this work, we aim to use the optical amplifiers, directional couplers and phase modulators to build the electro-optical gates. Thanks to the 2-layer-multilayer-perceptron structure, the inversion of matrix is performed to obtain the coupling ratio of the directional couplers and the phase delay of the phase modulators. The electro-optical OR, AND, XOR, NAND, NOR and XNOR gates are demonstrated. Moreover, we not only study the results under the ideal condition of device, but also discuss the imperfect situation with 1% error of fabrication or operation to study the tolerance of this system. Through our simulation results, the visibility of the gate output can be higher than 0.83. The gates can be fabricated in a silicon-based chip to develop the integrated optics computing system.

Nematic bits and universal logic gates.

Liquid crystals (LCs) can host robust topological defect structures that essentially determine their optical and elastic properties. Although recent experimental progress enables precise control over nematic LC defects, their practical potential for information storage and processing has yet to be explored. Here, we introduce the concept of nematic bits (nbits) by exploiting a quaternionic mapping from LC defects to the Poincaré-Bloch sphere. Through theory and simulations, we demonstrate how single-nbit operations can be implemented using electric fields, to construct LC analogs of Pauli, Hadamard, and other elementary logic gates. Using nematoelastic interactions, we show how four-nbit configurations can realize universal classical NOR and NAND gates. Last, we demonstrate the implementation of generalized logical functions that take values on the Poincaré-Bloch sphere. These results open a route toward the implementation of classical digital and nonclassical continuous computation strategies in topological soft matter systems.

New structure for an all-optical logic gate based on hybrid plasmonic square-shaped nanoring resonators and strips

Seven all-optical logic gates based on hybrid plasmonic squared-shaped nanoring resonators and strips are proposed, designed, and numerically analyzed using finite element method with COMSOL software package version 5.5. Constructive and destructive interferences between the input port(s) and the control port(s) are the main operating principles used to produce the proposed gates. The ratio of output optical power to the input power at a single port which is called the transmission threshold is selected to be 30% and the resonance wavelength is 1310 nm. All the hybrid plasmonic logic gates are performed in a single structure of 400 nm × 400 nm dimensions and the performance is measured according to the values of transmission at the output port versus a wavelength range from 800 to 2000 nm, contrast ratio, modulation depth, and insertion loss. The transmission exceeds 100% in five gates, 146% at NOT and NAND gates, 202.3% at OR, AND, and XNOR gates. The modulation depth scores are 99.75% at the XNOR gate, 98.5% at the NOR gate, 97.67% at OR, AND, NOT, and NAND gates, and 95.29% for the XOR gate.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

Tunable and Reconfigurable Logic Gates With Electrolyte-Gated Transistor Array Co-Integrated With Neuromorphic Synapses

A tunable and reconfigurable logic gates based on an electrolyte-gated transistor (EGT) array are co-integrated with neuromorphic synapses. The tunable and reconfigurable operations of the various logic gates are controlled by analog conductance modulation with nonvolatility of the fabricated EGT. The EGT array was uniformly fabricated on an entire 4-in wafer with the aid of CMOS compatible processes. Initiated-chemical vapor deposition (i-CVD) method was adopted for the deposition of the ultrathin polyethylene glycol dimethacrylate (pEGDMA) electrolyte layer. Therefore, the logic gates could be co-integrated with synaptic devices on the same in-plane substrate for integrability. Basic inverter operation with switching threshold tunability ranging from −1 to +1 V was demonstrated with good operational stability. In addition, NAND and NOR gate operations were realized by modulating the conductance level of a specified cell in the array configuration.

Power Efficient Technique for CMOS- Logic Circuits

Power outages on normal CMOS circuit is very high it can be reduced by using the adiabatic technique. Adiabatic technique is used in the pull up part of CMOS logic. Power loss of CMOS Logic is in terms of heat. Adiabatic is an efficient technique where some of the energy stored in the load and it is used for next inputs without dissipating as heat. The adiabatic technique depends largely on the parameter variation. With the help of DSCH, MICROWIND, TANNER EDA (S-edit, TWV, TSP) Software’s power consumed by ECRL (Efficient Charge Recovery Logic) is compared to the power consumed by common CMOS for NAND and NOR inverter circuits. In this study it is find out that the adiabatic technique is the good choice rather than conventional technique in terms of power consumption.

Realization of the skyrmionic logic gates and diodes in the same racetrack with enhanced and modified edges

Magnetic skyrmions are topological quasiparticles with nanoscale size and high mobility, which have potential applications in information storage and spintronic devices. Here, we computationally investigate the dynamics of isolated skyrmions in a ferromagnetic racetrack, where magnetic properties of the edges are enhanced and modified, forming a channel with lower magnetic anisotropy for skyrmion motion. It is found that the rectangular notch at the edge can have a pinning effect on the skyrmion and enrich the dynamics of the skyrmion. Based on the racetrack with modified edges and the notch, we design a racetrack that realizes the skyrmionic logic AND, OR, and NOT gates as well as the diode in the same magnetic racetrack. It is found that the driving current density could be much smaller than those used in previous designs of skyrmion-based logic gates. By slightly altering the shape of the racetrack, we also design the NAND and NOR gates. Finally, we study the feasibility of our design at finite temperatures. Our results may contribute to the design of nonvolatile spintronic devices with integrated multiple functions and ultra-low energy consumption.