Flash Memory Research Articles

Low-temperature etching of silicon oxide and silicon nitride with hydrogen fluoride

Etching of high aspect ratio features into alternating SiO2 and SiN layers is an enabling technology for the manufacturing of 3D NAND flash memories. In this paper, we study a low-temperature or cryo plasma etch process, which utilizes HF gas together with other gas additives. Compared with a low-temperature process that uses separate fluorine and hydrogen gases, the etching rate of the SiO2/SiN stack doubles. Both materials etch faster with this so-called second generation cryo etch process. Pure HF plasma enhances the SiN etching rate, while SiO2 requires an additional fluorine source such as PF3 to etch meaningfully. The insertion of H2O plasma steps into the second generation cryo etch process boosts the SiN etching rate by a factor of 2.4, while SiO2 etches only 1.3 times faster. We observe a rate enhancing effect of H2O coadsorption in thermal etching experiments of SiN with HF. Ammonium fluorosilicate (AFS) plays a salient role in etching of SiN with HF with and without plasma. AFS appears weakened in the presence of H2O. Density functional theory calculations confirm the reduction of the bonding energy when NH4F in AFS is replaced by H2O.

Comparing visio-spatial intelligence in amateur rugby and netball players using hand-eye coordination tests

Background: Research investigating the differences in visio-spatial skills (VSS) between athletes and non-athletes, as well as variations across sports, presents conflicting findings.Aim: The objective of this study was to determine if there exist significant differences in visio-spatial intelligence (VSI) skills between rugby players and netball players, and whether such disparities are present when comparing both groups to non-athletes.Setting: All participants, including the control group (non-athletes), rugby players and netball players, were recruited from the Zululand region of South Africa’s KwaZulu-Natal province, specifically from all premier league rugby and netball teams in the area.Methods: Participants underwent an optometric assessment, followed by an evaluation of VSS using six established tests: The Hart Near Far Rock, saccadic eye movement, evasion, accumulator, flash memory and ball wall toss tests.Results: The results revealed that rugby players significantly outperformed netball players in speed of recognition, peripheral awareness and hand-eye coordination (P = 0.000). Moreover, both rugby players and netball players performed significantly better than non-athletes in five of the six tests (P = 0.000), with the exception being the visual memory test (P = 0.809).Conclusion: This discrepancy in performance suggests that certain VSS are superior in athletes compared to non-athletes, highlighting potential implications for theories of vision, test selection and the development of sport-specific VSS testing batteries. Furthermore, the use of a hand-eye coordination-specific VSS test battery effectively differentiated between different sports.Contribution: The identified pattern was not consistent across all VSS tests, indicating that further research should explore the training methods employed by both sports, as these factors may contribute to the observed differences.

Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing

Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing

TinyML-Based Lightweight AI Healthcare Mobile Chatbot Deployment.

In healthcare applications, AI-driven innovations are set to revolutionise patient interactions and care, with the aim of improving patient satisfaction. Recent advancements in Artificial Intelligence have significantly affected nursing, assistive management, medical diagnoses, and other critical medical procedures. Many artificial intelligence (AI) solutions operate online, posing potential risks to patient data security. To address these security concerns and ensure swift operation, this study has developed a chatbot tailored for hospital environments, running on a local server, and utilising TinyML for processing patient data. Edge computing technology enables secure on-site data processing. The implementation includes patient identification using a Histogram of Gradient (HOG)-based classification, followed by basic patient care tasks, such as temperature measurement and demographic recording. The classification accuracy of patient detection was 95.8%. An autonomous temperature-sensing unit equipped with a medical-grade infrared temperature scanner detected and recorded patient temperature. Following the temperature assessment, the tinyML-powered chatbot engaged patients in a series of questions customised by doctors to train the model for diagnostic scenarios. Patients' responses, recorded as "yes" or "no", are stored and printed in their case sheet. The accuracy of the TinyML model is 95.3% and the on-device processing time is 217 ms. The implemented TinyML model uses only 8.8Kb RAM and 50.3Kb Flash memory, with a latency of only 4 ms. Each patient was assigned a unique ID, and their data were securely stored for further consultation and diagnosis via hospital management. This research demonstrates faster patient data recording and increased security compared to existing AI-based healthcare solutions, as all processes occur within the local host.

Operation Scheme Optimizations to Achieve Ultrahigh Endurance (1010) in Flash Memory

Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10¹⁰) in Flash Memory

Comprehensive investigations on defects’ stability caused lateral charge loss in Ti-doped 3D NAND

The comprehensive investigations on defects’ stability caused lateral charge loss are investigated in Ti-doped 3D NAND. The detailed study shows that the Ti-doping strategy could reduce pre-existing shallow traps in pure Si3N4. The stability of TiSi and Tii defects are observed under program/erase stress, but unstable TiN defects with shallow-trap levels (0.41 eV) also occur. Based on unstable defects, the device simulations are carried out revealing its effects on lateral charge loss, which indicates that TiN defects should be reduced for reliability. Our results strongly suggest the stability of Ti-related defects could be key points for lateral charge loss.

Mixed-Field Radiation of 3-D MLC Flash Memories for Space Applications

Mixed-Field Radiation of 3-D MLC Flash Memories for Space Applications

A Study of Flash Memory Type Synaptic Single Devices Manufactured Using Gold Particles

A Study of Flash Memory Type Synaptic Single Devices Manufactured Using Gold Particles

An Overview of the Future of Memory Cells: Advances in SSD Technology

This paper explores the topic of Solid-State Drives (SSDs) and NAND flash memory. Information of this paper is mainly obtained from authoritative academic websites and papers related to SSDs and flash memory. Memory cells are fundamental components in various electronic devices. In the field of data storage, SSDs represent the latest generation of storage devices, offering significantly better performance and functionality than traditional hard disk drives (HDDs). NAND flash memory chips are crucial component of SSDs, particularly 3D NAND, which exhibits exceptional performance and holds significant potential for future advancements. This paper will commence by providing an overview of SSDs and HDDs, followed by a comparison between NAND flash and NOR flash, and ultimately analysing the future of NAND flash memory technology employed in SSDs, with a focus on elucidating the advantages of 2D NAND over 3D NAND. Additionally, this paper explains a few challenges that NAND technology faces currently, as well as some possible solutions.

Intelligence data acquisition based on embedded system in Chinese cuisine cooker (CCICR V1.0)

The Chinese cooking process, intricate and diverse, encompasses a wide range of dishes, generating substantial data that often poses significant challenges for automation. To address these challenges, this paper introduces a versatile, highly reliable, user-friendly, and intelligent data recorder specifically designed for Chinese cuisine-the Chinese Cuisine Intelligent Cooker Recorder-V1.0 (CCICR-V1.0). This device is intended to record data generated during the cooking process and provide essential support for intelligent cooking robot systems. The core of CCICR-V1.0 is a STM32 microcontroller, equipped with sensors that monitor temperature, pressure, and attitude. These sensors facilitate the intelligent collection of data related to dishes, ingredients, and the movements of cookware throughout the cooking process. To ensure efficient data acquisition and storage, CCICR-V1.0 employs a multi-task data buffering storage method that effectively allocates CPU resources. NAND Flash is used as the storage medium, guaranteeing secure storage, management, and preservation of high-frequency, multi-channel data. Experimental results demonstrate the effectiveness of CCICR-V1.0 in achieving multi-channel, high-frequency data acquisition and storage in complex environments. This leads to an increase in automation efficiency of 89.9%. The weighing module demonstrates a maximum relative error of only 0.288%, while the attitude sensor experiment shows an attitude information error of just 0.22°C. Furthermore, the non-contact infrared temperature measurement module exhibits impressive performance with a maximum absolute error of 0.258∘C\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$^\\circ C$$\\end{document} and a maximum relative error of 0.88%. Notably, this measurement module has achieved a cost reduction of approximately 91.7% and an accuracy improvement of around 40%. Additionally, the response time of CCICR-V1.0 is less than 3 ms. With its ability to effectively capture data related to Chinese cooking, CCICR-V1.0 holds commercial value for widespread adoption and application in the field of intelligent cooking.

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Charge-Selective 2D Heterointerface-Driven Multifunctional Floating Gate Memory for In Situ Sensing-Memory-Computing.

Flash memory, dominating data storage due to its substantial storage density and cost efficiency, faces limitations such as slow response, high operating voltages, absence of optoelectronic response, etc., hindering the development of sensing-memory-computing capability. Here, we present an ultrathin platinum disulfide (PtS2)/hexagonal boron nitride (hBN)/multilayer graphene (MLG) van der Waals heterojunction with atomically sharp interfaces, achieving selective charge tunneling behavior and demonstrating ultrafast operations, a high on/off ratio (108), extremely low operating voltage, robust endurance (105 cycles), and retention exceeding 10 years. Additionally, we achieve highly linear synaptic potentiation and depression, and observe the reversibly gate-tunable transitions between positive and negative photoconductivity. Furthermore, we employed the VGG11 neural network for in situ trained in-sensor-memory-computing to classify the CIFAR-10 data set, pushing accuracy levels comparable to pure digital systems. This work could pave the way for seamlessly integrated sensing, memory, and computing capabilities for diverse edge computing.

Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.

We aimed to fabricate reliable memory devices using HfO2, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (Dit) reached a minimum value of 1.0 × 1012 eV-1cm-2. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO2/HfO2 interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.

A Study on the Channel Holes’ Diameter Effects of High-Performance Vertical-Channel Flash Memory Cells

Abstract High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/ Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

Resource-optimized cnns for real-time rice disease detection with ARM cortex-M microprocessors

This study explores the application of Artificial Intelligence (AI), specifically Convolutional Neural Networks (CNNs), for detecting rice plant diseases using ARM Cortex-M microprocessors. Given the significant role of rice as a staple food, particularly in Malaysia where the rice self-sufficiency ratio dropped from 65.2% in 2021 to 62.6% in 2022, there is a pressing need for advanced disease detection methods to enhance agricultural productivity and sustainability. The research utilizes two extensive datasets for model training and validation: the first dataset includes 5932 images across four rice disease classes, and the second comprises 10,407 images across ten classes. These datasets facilitate comprehensive disease detection analysis, leveraging MobileNetV2 and FD-MobileNet models optimized for the ARM Cortex-M4 microprocessor. The performance of these models is rigorously evaluated in terms of accuracy and computational efficiency. MobileNetV2, for instance, demonstrates a high accuracy rate of 97.5%, significantly outperforming FD-MobileNet, especially in detecting complex disease patterns such as tungro with a 93% accuracy rate. Despite FD-MobileNet’s lower resource consumption, its accuracy is limited to 90% across varied testing conditions. Resource optimization strategies highlight that even slight adjustments, such as a 0.5% reduction in RAM usage and a 1.14% decrease in flash memory, can result in a notable 9% increase in validation accuracy. This underscores the critical balance between computational resource management and model performance, particularly in resource-constrained settings like those provided by microcontrollers. In summary, the deployment of CNNs on microcontrollers presents a viable solution for real-time, on-site plant disease detection, demonstrating potential improvements in detection accuracy and operational efficiency. This study advances the field of smart agriculture by integrating cutting-edge AI with practical agricultural needs, aiming to address the challenges of food security in vulnerable regions.

TeraHeap: Exploiting Flash Storage for Mitigating DRAM Pressure in Managed Big Data Frameworks

Big data analytics frameworks, such as Spark and Giraph, need to process and cache massive datasets that do not always fit on the managed heap. Therefore, frameworks temporarily move long-lived objects outside the heap (off-heap) on a fast storage device. However, this practice results in (1) high serialization/deserialization (S/D) cost and (2) high memory pressure when off-heap objects are moved back for processing. In this article, we propose TeraHeap , a system that eliminates S/D overhead and expensive GC scans for a large portion of objects in analytics frameworks. TeraHeap relies on three concepts: (1) It eliminates S/D by extending the managed runtime (JVM) to use a second high-capacity heap (H2) over a fast storage device. (2) It offers a simple hint-based interface, allowing analytics frameworks to leverage object knowledge to populate H2. (3) It reduces GC cost by fencing the collector from scanning H2 objects while maintaining the illusion of a single managed heap, ensuring memory safety. We implement TeraHeap in OpenJDK8 and OpenJDK17 and evaluate it with fifteen widely used applications in two real-world big data frameworks, Spark and Giraph. We find that for the same DRAM size, TeraHeap improves performance by up to 73% and 28% compared to native Spark and Giraph. Also, it can still provide better performance by consuming up to \(4.6\times\) and \(1.2\times\) less DRAM than native Spark and Giraph, respectively. TeraHeap can also be used for in-memory frameworks and applying it to the Neo4j Graph Data Science library improves its performance by up to 26%. Finally, it outperforms Panthera, a state-of-the-art garbage collector for hybrid DRAM-NVM memories, by up to 69%.

Deep Learning Algorithms for Cryptocurrency Price Prediction: a Comparative Analysis

Over the past years, cryptocurrencies have experienced a surge in popularity within the financial markets. As of today, besides being considered for investment purposes, they also serve as a widely accepted form of currency for everyday transactions. Due to the intricate characteristics of financial markets and their dependence on various factors to determine the prices of stocks and assets, the ability to predict such price is crucial to make investment choices, especially in terms of cryptocurrencies. In this work, a comparative analysis on the suitability of Deep Learning (DL) algorithms (effective for time series forecasting) in predicting the price of three cryptocurrencies (namely: Bitcoin, BTC; Ethereum, ETH; and Ripple, XRP) is assessed in terms of both short-term and long-term prediction accuracy. The results, evaluated using Root Mean Square Error (RMSE), Mean Absolute Error (MAE), Mean Absolute Percentage Error (MAPE), and coefficient of determination (denoted as \(R^{2}\) ), reveal that: Transformer is generally more effective for short-term forecasts and also performs well for long-term predictions; Convolutional Neural Network-Recurrent Neural Network (CNN-RNN) demonstrates the lowest complexity in terms of number of Multiply and ACcumulate (MAC) operations; SimpleRNN has the fewest parameters and the smallest FLASH memory requirement. Overall, CNN-Gated Recurrent Unit (CNN-GRU) provides the best joint accuracy-complexity for predicting BTC and ETH prices, whereas CNN-RNN yields superior results for XRP price prediction.

Thermal atomic layer deposition-processed InHfZnO thin film transistors with excellent stability

In recent years, the downscaling of transistors has sparked considerable interest in the advancement of amorphous oxide semiconductors, particularly indium-hafnium-zinc oxide (IHZO) has remarkable potential in applications such as high-resolution displays and 3D NAND. For the first time, we propose the fabrication of IHZO thin film transistors (TFTs) via thermal atomic layer deposition (TH-ALD). The preparation, electrical properties, and stability of IHZO TFTs are investigated. The performance of TFT deposited at 250 °C and annealed in N2 atmosphere at 300 °C exhibits a high field-effect mobility (μ) of 22.53 cm2/Vs, a high Ion/Ioff of ∼107, a low threshold voltage (Vth) of 0.15 V, and a minimum subthreshold swing (SS) of 0.24 V/decade. Furthermore, the threshold voltage shifts (ΔVth) in TFTs annealed in N2 and O2 are 0.31 and 0.16 V, respectively. These enhancements are attributed to the defects suppression and remaining ionized oxygen vacancies result in increased electron concentration in N2-annealed films. In comparison, O2 annealing causes a reduction in field effect mobility but concurrently enhances stability due to the direct passivation of defects, which leads to fewer oxygen vacancies. Additionally, Hf content can also impact the performance of TFT devices, even a small addition of Hf also results in the effective reduction of the carrier concentration. These findings provide valuable insights into the device mechanism of IHZO TFTs, presenting a novel avenue for comprehending and augmenting their overall performance.

Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate.

In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-VTH (HVT) state and the screening of the applied field by the channel at the low-VTH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.

Reversing File Access Control Using Disk Forensics on Low-Level Flash Memory

In the history of access control, nearly every system designed has relied on the operating system (OS) to enforce the access control protocols. However, if the OS (and specifically root access) is compromised, there are few if any solutions that can get users back into their system efficiently. In this work, we have proposed a novel approach that allows secure and efficient rollback of file access control after an adversary compromises the OS and corrupts the access control metadata. Our key observation is that the underlying flash memory typically performs out-of-place updates. Taking advantage of this unique feature, we can extract the “stale data” specific for OS access control, by performing low-level disk forensics over the raw flash memory. This allows efficiently rolling back the OS access control to a state pre-dating the compromise. To justify the feasibility of the proposed approach, we have implemented it in a computing device using file system EXT2/EXT3 and open-sourced flash memory firmware OpenNFM. We also evaluated the potential impact of our design on the original system. Experimental results indicate that the performance of the affected drive is not significantly impacted.