NAND Flash Memory Research Articles

Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory

Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory.

Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).

3D NAND Based on Conventional Flash Memory Architecture Research and Application Prospects

With the rapid development of computer technology as a whole, the performance requirements of modern computer systems for storage technology are becoming higher and higher. This paper discusses the response to the problems that have arisen with the traditional storage in today's era, that is, the construction principle of the new storage three-dimensional memory (3D NAND) and the future development. Traditional storage in order to enhance the storage space of the plane flash memory, can only be components for shrinking, when shrinking to a certain extent when the flash memory will occur uncontrollable hidden danger, so the invention of 3D NAND. By vertically stacking many layers of memory cells, the storage density per unit area is greatly increased, with high-speed reading and writing, large capacity, low power consumption and other characteristics. Nowadays, 3D NAND is widely used in enterprises, and the industry is hopeful about the long-term prospects of the growing global demand for data generation and storage and the introduction of new technologies. The development of 3D NAND technology provides higher storage density and lower cost for NAND flash memory to meet the growing demand for data storage. This paper provides a systematic summary of existing research on 3D NAND in the hope that it will better enhance the overall technology improvement in the storage industry.

Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance

Although NAND flash memory does a lot of work in effectively using Error Correcting Code(ECC) to reduce Uncorrectable Bit Error Rate(UBER). However, if the Frame Error Rate(FER) is not reduced, the lower UBER cannot effectively reduce the read latency of the flash memory system. This phenomenon is especially evident at the end of the flash memory lifetime, where conventional methods significantly reduce the UBER but not to zero, and the remaining error bits are still evenly distributed throughout the flash memory page, resulting in a significant increase in read latency. In this paper, an interleaved LDPC decoding scheme is proposed. By re-evaluating the flash memory channel during the decoding process, the codewords in the flash memory page are corrected frame by frame, and the problem of high FER is solved at the end of the flash memory lifetime. Compared with the conventional algorithm, the proposed method can reduce the FER by up to 34%, reduce the average decoding iterations by 63.4%, and reduce the read latency by up to 65%.

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory.

The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.

Modeling of 3D NAND Characteristics for Cross‐Temperature by Using Graph Neural Network and Its Application

Herein, the impact of cross‐temperature on 3D NAND flash memory is modeled by considering adjacent cells using machine learning. The cells comprising NAND flash memory exhibit diverse states and connectivity patterns. To effectively capture this complexity, the 3D NAND flash is converted to graph structure and the graph neural network (GNN) is leveraged, known for its exceptional performance in handling graph data. To the best of the authors' knowledge, this is the first attempt to model 3D NAND flash memory using GNN. This method has good generalization performance across various retention times and temperatures, achieving a remarkable overlap of 95.28% between ground truth and predicted distributions. Moreover, two applications of this method are introduced that contribute to the NAND flash memory improvement. One is a GNN‐assist program, which leverages well‐trained GNN to suppress the degradation affected by cross‐temperature, resulting in reduced shift and narrower distribution width. The other is the sensitivity decomposition to identify parameters influencing the cell at cross‐temperature. It is found that cross‐temperature impact extends beyond physically connected cells to adjacent cells at close distances. Overall, this work provides valuable insights into modeling 3D NAND flash memory using GNNs and offers practical methods for enhancing NAND flash memory reliability.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.

Improved impedance matching speed with gradient descent for advanced RF plasma system

Plasma processes are widely used in the fabrication of integrated circuits for the smaller, faster, more powerful circuits demanded by new technology. High-performance semiconductor equipment is required for dynamic random-access memory and three-dimensional NAND flash memory in semiconductor manufacturing. To enhance the speed of RF impedance matching, this paper proposes a method for calculating the load impedance of the plasma chamber. To calculate the target value of the variable components, we employ the input impedance of the impedance-matching unit and the complex impedances of the variable components. In addition, the internal parameters are automatically tuned through the gradient-descent method of machine learning, which improves the accuracy of impedance matching. The new matching method achieved a fast matching time and high efficiency of the matching trajectories. Moreover, it avoids the increase of the reflected power during the matching process, which causes plasma instability, and prohibits significant matching delay in a specific area, which disadvantages the conventional matching algorithm. These advantages are expected to significantly expand the development of new plasma processes from that of conventional impedance matching.

Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash

We propose a new voltage scheme for string-select (SS) transistors to improve inhibition characteristics of unselected cells during selective 1-bit erase in vertical NAND flash memory. Different from the reported schemes, we apply different control voltages to each of the three SS transistors of unselected drain select lines and all source select lines to lower the channel potential. The change in the channel potential depending on the voltage of the SS transistors and the resulting gate-induced drain leakage is explained via TCAD simulation. The proposed pulse method can reduce the Vth of the 1-bit cell selected for erase by 168% compared to the reported method while maintaining the same inhibition characteristics.

High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage

3D NAND flash memory is the ubiquitous non-volatile memory (NVM) on the market because of its large storage capacities, high reliability, and low bit-cost. The reliability characteristics of 3D NAND flash memory, however, are considerably different from those of 2D NAND flash memory due to the peculiar architectures. In this paper, read disturb (RD) at various program/erase (P/E) stages is thoroughly explored. To adjust the low-density parity check (LDPC) codes dynamically and extend the lifetime of 3D NAND flash memory, short-term lifetime prediction models of RD and endurance are proposed based on in-depth studies on the correlations of fail bit count (FBC) at various lifetime stages, and their accuracy is tested experimentally. A new short-term warning system (STWS) is proposed to extend the lifetime of 3D NAND-based storages. It consists of the error-bits’ prediction module (EBPM) and the self-adjustable low-density parity check codes module (SLDPC), where EBPM predicts FBC periodically and SLDPC pre-allocates LDPC codes for future use based on the result of EBPM. The experimental result shows that our prediction models have high reliability, and STWS can effectively prolong the lifetime of NAND flash. The findings of this study provide fundamental insights into FBC degradation in 3D NAND flash, as well as a simple and practical method for building 3D NAND-based storage with high reliability.

Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory

Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory

LDPC Level Prediction Toward Read Performance of High-Density Flash Memories

High-density NAND flash memories have been prevailing in storage systems to achieve large capacities for explosive data. However, they suffer from more severe reliability degradation due to the narrowed margins between threshold voltage states. LDPC codes have been widely applied in high-density flash memories to ensure data reliability. Due to the increased number of cell states, more read voltages are required in reading a flash page correctly. This induces more soft levels to read pages with high bit error rates in LDPC decoding. Read latency is significantly increased in high-density flash memories. To enhance the read performance of high-density flash memories, this paper proposes PreLDPC, an LDPC level prediction approach with fine-grained LDPC reading. The key idea of PreLDPC is to predict the final read level during the early read iteration, thus avoiding unnecessary read-retry latency. From a preliminary study, we observe that after decoding in the first two iterations, the ratio of cells that lie in error-prone area (i.e. adjacent area of two cell states) can be obtained. The ratio is closely related to the final read level for a successful decoding. By exploiting this observation, PreLDPC directly uses the predicted read level for LDPC reading, which could eliminate excessive number of read retries. Furthermore, by exploiting the benefit of fine-grained LDPC reading, this paper further divides the existing integer level (called i-level, e.g. level-1 and level-2) into finer decimal level (called d-level, e.g. level-1.25 and level-1.5), and proposes a fine-grained read method. By combining the prediction method and fine-grained method together, PreLDPC can first estimate the i-level and then perform the read-retry iteration with d-levels to eliminate unnecessary read latency as much as possible. From experimental results of real-world workloads on Disksim with SSD extensions, it is verified that PreLDPC can effectively reduce read latency in high-density flash memories.

An all-digital built-in-self-test scheme for duty cycle corrector with de-skew circuit in NAND Flash memory

This paper presents an all-digital built-in-self-test (BIST) scheme to quickly test the duty cycle corrector (DCC) with de-skew circuit in NAND Flash memory. The proposed BIST circuit adopts an adjustable duty cycle module to generate the input signal of DCC, then it utilizes a high-resolution vernier time-to-digital converter to quantify the pulse widths related to duty cycle and phase difference into digital codes. The proposed BIST scheme can quickly obtain accurate measurement results of the input/output duty cycle of DCC and the phase difference of signals without using high-precision test equipment, it is a low-cost built-in testing solution for NAND Flash memory. The test chip is fabricated using 130 nm CMOS process. The area occupies 0.0425 mm2, and the proposed circuit consumes 2 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. The experimental results show that the measurement error of duty cycle is in the range of −0.85% to 1.5% and the measurement error of phase difference is within ±6 ps.

Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability

Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.

Method for improving dry etching end point detection based on change in time accumulation correlation of plasma emitting wavelengths

This study proposes an optical emission spectroscopy (OES) analysis methodology to improve the ability to detect etching endpoints during high-level semiconductor plasma etching processes. Representative etching endpoint detection methods using single wavelength intensity or multiple wavelength intensity ratio changes include a low signal-to-noise ratio, high plasma instability, a small etching open area, and weak by-product emission signal problems due to deep etching under high-level process conditions such as high aspect ratio contact etching (HARC). As a result, it is difficult to detect the etching endpoint due to the very small or noisy change in the intensity over time due to the process progress of the wavelength selected by OES to detect the etching endpoint. In this study, a method of deriving an accumulative time correlation value according to process progress between selected wavelengths was developed by selecting all wavelengths observed in a specific wavelength region such as ultraviolet region in a spectrum emitted from plasma during a plasma etching process. After classifying the entire correlation signal groups derived as a pair of two intensity peak wavelengths into a dynamic time wrapping algorithm, the intensity change rate of the signal according to the process time was observed by selecting the signal with the most sensitive time change rate during the process. During the vertical nand flash memory manufacturing process, a test wafer for the purpose of detecting the etching endpoint was manufactured and evaluated under the conditions of the cell metal contact etching process, which is a high-level HARC etching process. As a result, it was confirmed that the signal selected by deriving the time accumulative correlation method had a high intensity change rate and a signal-to-noise ratio over time compared to a single wavelength or a plurality of wavelength ratio signals. The method proposed in this study is expected to contribute to process optimization by contributing to improving the ability to detect etching endpoints in high-level plasma etching processes in the future.

A novel gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance with disturbance-less program operation

In this paper, we propose a gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance and reliability. First, in the selected string, we confirmed that the proposed structure can improve program performance using negative bit-line voltage scheme with pass disturbance-less characteristic. Second, in the inhibited string, we confirmed self-boosting, which is perfectly performed by the back-gate bias without the unselected WL. Based on these potentials of the GAAB NAND structure, we would like to propose our GAAB structure as a future structure with the advantages of high performance and high reliability characteristics compared with conventional GAA-type NAND flash memory.

Optimization of Process Parameters on Short-Term Retention for Charge-Trapping 3-D NAND Flash Memories Using Novel Neural Networks Approach

Optimization of Process Parameters on Short-Term Retention for Charge-Trapping 3-D NAND Flash Memories Using Novel Neural Networks Approach

CRFTL: Cache Reallocation-Based Page-Level Flash Translation Layer for Smartphones

Because of its outstanding performance, NAND flash memory in the form of embedded flash drives like Universal Flash Storage (UFS) has been widely used in the modern smartphones. As the core software in UFS, the flash translation layer (FTL) is essential to the performance improvement of UFS. To consider all workloads, a balanced and fixed mapping cache allocation scheme is used in the existing FTLs. Confronted with frequent changes of I/O request patterns of applications in smartphones, the existing FTLs with the fixed mapping cache allocation scheme could not perform well. To consider the I/O characteristics of smartphones, a novel cache reallocation-based page-level flash translation layer, called CRFTL, is proposed in this paper. Through analyzing the life cycle of I/O requests of applications in smartphones, CRFTL stores the mapping entries of I/O requests with different life cycles in different mapping cache structures. CRFTL can be aware of the inner states of NAND flash memory and I/O request patterns, and adaptively adjusts the cache space allocation of the mapping cache structures by applying the approach combining the heuristics and reinforcement learning algorithms. The experimental results show that the performance of our proposed CRFTL is better than that of existing FTLs.

An Efficient Hot-Cold Data Separation Garbage Collection Algorithm Based on Logical Interval in NAND Flash-Based Consumer Electronics

In NAND flash-based consumer electronics, garbage collection can degrade consumer electronics performance. And the extra page writes caused by garbage collection reduce the lifespan of consumer electronics. Hot-cold data separation has a critical impact on garbage collection. Therefore, inaccurate hot-cold data separation significantly affects garbage collection overhead and the performance of wear leveling. In addition, accurate data separation depends greatly on heat calculation of each page in NAND flash and extra memory is required to record page heat information. In this paper, we propose an efficient and novel hot-cold data separation garbage collection algorithm. The proposed algorithm introduces T-P factor which combines update time and page sequence number to calculate the heat of different logical interval rather than page, thus accurate hot-cold data separation can be achieved. Based on T-P factor, garbage collection strategy is improved accordingly. Experimental results show that the proposed algorithm is superior to existing algorithms in terms of garbage collection overhead, wear leveling and extra memory consumption in NAND flash-based consumer electronics.

A Granularity-Based Clustering Method for Reducing Write Amplification in Solid-State Drives

In recent years, solid-state drives (SSDs) that adopt NAND flash memory have been widely used as the main storage devices. In particular, NAND flash memory has a special feature of “out-of-place” updates to write the up-to-date data to a free page, and the corresponding old page will become invalid. When the number of free pages in SSDs is insufficient, garbage collection (GC) will be executed to reclaim the invalid pages in a block by erasing the block. Many studies have shown that a good hot/cold data separation (i.e., clustering) can greatly reduce the overhead of GC so as to improve the SSD performance. However, previous clustering methods usually use a static number of clusters or a fixed size of granularity (i.e., a fine-grained or a coarse-grained granularity), so they may not always perform well for different kinds of workloads. Therefore, we propose a granularity-based clustering method to adaptively adjust the size of granularity groups for an appropriate number of clusters at runtime according to the update distances of logical addresses. According to the experimental results, we can improve SSD performance by reducing the overhead of GC and decrease the write amplification. Furthermore, we can show that the proposed method can utilize a fine-grained granularity to retain the record accuracy of update distances and also utilize a coarse-grained granularity to reduce the space required to record update distances.