NAND Devices Research Articles

Atomic Layer Etching of Al2O3 Using F Radical and Al Precursors: Surface Reaction and Reaction Mechanism Study

In order to overcome the miniaturization of semiconductor devices, devices with a three-dimensional (3D) structure, such as FinFET and 3D vertical NAND devices, were introduced. The manufacturing of 3D devices requires both anisotropic etching in the vertical direction and isotropic etching in the horizontal direction. Therefore, a new technology with atomic-level precision is required for isotropic etching, which is dependent on wet etching. It is the thermal atomic layer etching (ALE) process that meets these requirements. Since the first report in 2016, the thermal ALE processes by alternating exposures to HF vapor and a metal precursor have been reported for various thin films. However, HF has issues with safety and corrosion. Recently, ALE processes using F radicals produced by inductively coupled plasma (ICP) of SF6 or NF3 have been reported [1,2]. However, the study on the reaction mechanism of F radicals is lacking. In this study, the surface reaction was studied for the modification and removal steps by NF3 remote plasma and Al precursors. We used quartz crystal microbalance (QCM) to measure the mass change during the ALE process and X-ray photoelectron spectroscopy (XPS) to analyze the composition of the modified layer. The mechanism of ALE using F radical was different from that using HF, due to the absence of H atoms. Density functional theory (DFT) simulation shows that amorphous carbon or fluorocarbon layer can be formed during the ALE by F radicals. Al precursor with fewer organic ligands was beneficial to suppress the formation of a carbon-containing surface layer. Acknowledgments This research was supported by the MOTIE (Ministry of Trade, Industry & Energy (project number 20012588) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Statistical Compact Modeling With Artificial Neural Networks

This work proposes a statistical modeling approach for the artificial neural network (ANN) based compact model (CM). The method of retaining part of the network features of the nominal device and further finetuning the network parameters (variational neurons) is found to accurately reproduce the static variation. A mapping from process variation to network parameters is derived by combining the proposed variational neuron selection algorithm and the backward propagation of variance (BPV) method. In addition, a secondary classification of the selected variational neurons is applied to model the fabrication-induced correlation between n-and p-type devices. The NN-based statistical modeling approach has been well implemented and verified on the GAA simulation data and the 16nm node foundry FinFET, which indicates its great potential in modeling emerging and advanced device technology.

Design Strategy to Improve Memory Window in Ferroelectric Transistors With Oxide Semiconductor Channel

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx layer between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.

Molecular dynamics simulation of oxide-nitride bilayer etching with energetic fluorocarbon ions

In 3D NAND devices, the number of stacked layers dictates the storage capacity. In the fabrication of such devices, hole channels with a high-aspect ratio (HAR) are etched through these layers. The higher the aspect ratio becomes, the more difficulties the HAR etching faces. In this study, molecular dynamics simulation was performed to examine the etching of silicon dioxide (SiO2), silicon nitride (SiN), and oxide-nitride (ON) stacked layers by energetic fluorocarbon ions. Good agreement of etching yields obtained from the simulations and ion beam experiments was observed for the etching of SiO2 and SiN by CF3+ ions for the incident ion energy ranging from 200 to 2000 eV. As to the etching of the ON bilayer, the SiO2 and SiN layers were observed to be etched with their own etch rates at low ion incident energy. However, at sufficiently high incident ion energy, the oxide and nitride layers were mixed by energetic ion impact and the depth of the mixing layer exceeded the thickness of the top SiO2 layer thickness, resulting in a single etch rate limited by the etch rate of a much deeper underlying SiN material. This suggests that if the incident ion energy is high enough such that the thicknesses of the multilayers are lower than the ion penetration depth, the ON stacked layer exhibits a single etch rate determined by the mixed material of the oxide and nitride.

Understanding of Etching Mechanism of Si3N4 Film in H3PO4 Solution For The Fabrication of 3D NAND Devices

Silicon nitride (Si3N4) has been widely used as an insulating or etch stop layer in the semiconductor devices [1]. For example, in a 3D V-NAND flash memory manufacturing process, Si3N4 is alternately stacked with silicon oxide (SiO2) to form a NAND structure. Here, it is necessary to selectively etch Si3N4 avoiding etching of SiO2 in the repeated Si3N4/SiO2 multi-stack layers. In general, phosphoric acid (H3PO4) is used to selectively etch Si3N4 against SiO2 [2]. However, since the concentration of H3PO4 solution changes with the evaporation of H2O, it is not easy to determine the concentration dependence of Si3N4 etching rate in H3PO4 solution. In order to properly control the shape of the 3D V-NAND structure, it is necessary to extensively understand the effect of H3PO4 concentration on the Si3N4 etching. The study of Si3N4 etching has been mainly focused on the effect of additives in H3PO4 on the behavior of Si3N4 etching to solve the issue such as oxide regrowth so far [3, 4]. Fundamental study of the Si3N4 etching reaction mechanism in H3PO4 is lacking. In this study, the Si3N4 etching mechanism in H3PO4 solution is elucidated systematically.For the investigation of Si3N4 etching reaction mechanism, LPCVD Si3N4 blanket wafer and Si3N4/SiO2 multi-stack layered trench wafer were used. Etching experiments of of Si3N4 were conducted in 10-95 wt% H3PO4 solutions at 160 °C. Spectroscopic ellipsometry and field emission scanning electron microscopy were used to measure the etching rate of Si3N4 after etching process.First, the changes in etching rate of Si3N4 in the various concentrations of H3PO4 solution were investigated. As shown in Fig. 1, according to our kinetic calculation and experiments, etching rate of Si3N4 increased as the H3PO4 concentration increased until the concentration of H3PO4 reaches a certain concentration that produced the highest etching rate. However, etching rate of Si3N4 decreased with the concentration of H3PO4 beyond the critical H3PO4 concentration. According to the results, there may be two concentrations of H3PO4 solution which produce an identical etching rate of Si3N4. It is also suggested that not only H3PO4 but also H2O plays an important role in the Si3N4 etching kinetics.To investigate the role of H2O and H3PO4 in the etching reaction of Si3N4, kinetic isotope effect (KIE) of Si3N4 etching reaction in H3PO4 solution was used. KIE provides information about which reactant determines the rate-limiting step. In this study, each reactant of Si3N4 etching reaction, H2O or H3PO4, was substituted with D2O and D3PO4, respectively. Then, etching of Si3N4 was conducted in four different solutions. As shown in Fig. 2, when H3PO4 was replaced by D3PO4, the Si3N4 etching rate was not significantly changed. However, when H2O was replaced by D2O, the Si3N4 etching rate decreased by 30 %. Therefore, it is thought that rate-limiting step of the Si3N4 etching reaction is determined by an elementary reaction related to H2O rather than H3PO4.Based on the above results, Si3N4 etching reaction mechanism was suggested. First, the Si3N4 surface termination (-NH2) is substituted with H2PO4 -, which is a weak nucleophile, by an SN1-like reaction. When H2PO4 - binds to Si, the backbone of Si3N4 is weakened because the electronegativity of O (3.44) is greater than N (3.04). Next, the Si-N of the weakened backbone of Si3N4 is substituted with Si-OH by an SN2-like reaction of H2O. This SN2-like reaction is considered as a rate-limiting step. It is believed that understanding of etching mechanism of Si3N4 in H3PO4 solution will improve selective etching process of Si3N4 for the integration of 3D V-NAND.

Understanding of Etching Mechanism of Si3N4 Film in H3PO4 Solution For The Fabrication of 3D NAND Devices

The etching mechanism of the Si3N4 in H3PO4 solution is proposed. The effect of H3PO4 concentrations on Si3N4 etching rate is investigated. The Si3N4 etching rate is not simply proportional to H3PO4. Both H3PO4 and H2O participate in the Si3N4 etching reaction and play their roles. First, H2PO4 - which is a weak nucleophile generated from H3PO4 replaces -NH2 on the Si3N4 surface with -H2PO4 by an SN1-like reaction. Next, N-Si which is backbone of Si3N4 network is substituted by H2O with Si-OH by an SN2-like reaction. From the Si3N4 etching mechanism and kinetic studies, it is concluded that the Si3N4 etching rate is proportional to product of concentration of H2O and H3PO4. These results suggest that consumption of H3PO4 can be reduced by using a lower concentration of H3PO4 between two H3PO4 concentrations that can produce a similar Si3N4 etching rates.

Total-Ionizing-Dose Effects on Polycrystalline-Si Channel Vertical-Charge-Trapping Nand Devices

Total-ionizing-dose effects are evaluated in vertical-charge-trapping NAND devices with silicon oxynitride (SiON) and SiO2 tunneling layers. Processing splits include SiON tunneling layers with and without H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> high-pressure annealing. Programmed devices were irradiated to 500 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with 10-keV X-rays and annealed for 30 min. Second programming after annealing does not fully restore the original, programmed state. Radiation-induced trapped holes compensate for deeply trapped electrons that are injected into the dielectric during device programming. Throughout the full irradiation and annealing sequence, threshold voltages remain large enough to enable successful nonvolatile (NV) memory application.

Unsupervised Learning in Winner-Takes-All Neural Network Based on 3D NAND Flash

Experimental demonstration of unsupervised learning is realized with charge-trapping 3D NAND flash device array. The charge-trapping characteristic of the memory cell is leveraged so that the devices perform not only as non-volatile memory but also synaptic cells in hardware neural network. Experiments reveal that the 3D NAND flash devices hold good potential for neuromorphic computing because of its delicately modulated synaptic weight. Furthermore, differential pair scheme is employed to enable larger dynamic range and finer weight tunability as compared with previous works. And based on the 3D NAND array, unsupervised learning is implemented by experiments with a winner-takes-all neural network, which can achieve perfect clustering of stylized letters within tens of training epochs. Beyond that, the 3D NAND devices also exhibit highly robust reliability against various disturb during synaptic weight update. The excellent synaptic device performance and reliability altogether make solid foundation for the winner-takes-all update rule in unsupervised learning neural network.

An Early-Life NAND Flash Endurance Prediction System

NAND flash memory – ubiquitous in today’s world of smart phones, SSDs (solid state drives), and cloud storage – has a number of well-known reliability problems. NAND data contains bit errors, which require the use of error correcting codes (ECCs). The raw bit error rate (RBER) increases with program-erase (P-E) cycling, and the number of P-E cycles the device can withstand before the RBER exceeds the ECC capability is called its endurance . ECC operates on data stored in a sector of NAND, and there is a large variation in the endurance of sectors within a device and across devices, resulting in excessively conservative endurance specifications. This research shows, for the first time, that a sector’s true endurance can be predicted with remarkable accuracy, using a combination of the sector’s location within the device, and measurements taken at the very beginning of life. Real-world data is gathered on millions of NAND sectors using a custom-built test platform. Optimised machine learning classification models are built from the raw data to predict if a sector will pass or fail to a fixed ECC threshold, after a target P-E cycling level has been reached. A novel technique is demonstrated that uses different ECC thresholds for model training and testing, which allows the models to be tuned so that they never misclassify samples that would fail. This eliminates ECC failures and data loss, allowing simpler, less expensive ECC schemes to be used for modern NAND devices. It also enables significant endurance extensions to be achieved.

(Invited) Theoretical Understanding of Nanoscale Ferroelectric Field-Effect-Transistor Having a Poly-Domain Structure

The emergence of ferroelectricity in doped HfO2 and (Hf,Zr)O2 (HZO) thin film with a typical thickness ~10 nm brings back the great interest in ferroelectric (FE) memories including the conventional ferroelectric random access memory, ferroelectric field-effect transistors (FEFET), and more recent negative capacitance field-effect transistors, in not only academia but also memory industry. In the industry, one of the most important issues concerning a FEFET is whether FEFET based NAND (FE-NAND) memory can be a next-generation device with superior performance to a conventional CTF-based NAND memory. For this purpose, it must have the multi-level capability and lower interference between adjacent memory cells. Because of sufficiently large ferroelectric polarization (10~15 uC/cm2 for typical HZO thin film), the multi-level capacity of FE-NAND would be higher than that of CTF-based NAND. However, an experimental result of FE-NAND devices shows that only a tenth of the expected memory window for the reading operation was achieved. At the same time, ten times larger erasing/writing voltages are required.In this work, we presented the comprehensive FEFET model to describe the writing process and reading process in FEFET from the fundamental viewpoint of metal-oxide-semiconductor (MOS) FET device physics in conjunction with the FE switching phenomenon. To capture the multi-domain nature of the ferroelectric thin film, we adopted the time-dependent Ginzburg-Landau (TDGL) formalism as a core physics of the switching kinetics. Furthermore, the FEFET model has been extended to a 3-Dimensional FE-NAND simulation. These models showed that the multi-domain nature of the ferroelectric film, which is shared by serial gates in the FE NAND device, not only degrades gate controllability on a target memory cell but also decreases a magnitude of surface potential. The extensive simulation results provided a critical view to understand the degraded memory window of FEFET and a possible strategy for the improvement.

3-D NAND Technology Achievements and Future Scaling Perspectives

Since the introduction of a 3-D NAND product in 2014, the areal density has increased by more than 8 times (from 0.96 to 7.80 Gb/mm2) in the recent five years. The increase of word-line (WL) stacking from 24 to 128 layers, the scaling of bits per cell from 2 to 3 bits/cell and 4 bits/cell, and a CMOS under array technology enabled this successful 3-D NAND density scaling. A gate-all-around cell architecture realized excellent reliability and program/read performance by having a large physical cell size and good shielding of cell-to-cell interference. In the newly introduced 3-D NAND devices, several new cell phenomena have been reported. Unique temperature dependence and threshold-voltage instability are observed due to the polysilicon channel. Down-coupling of the floating body and its impact on program disturb and hot electron injection were reported. The cell-to-cell interference is enhanced by the effective gate length modulation due to the no-lightly doped drain (LDD) string architecture. For the future 3-D NAND scaling, WL stacking will continue to be a key driver. In addition, XYZ dimension shrink of the cell will become another key critical scaling direction in order to relieve the cost and device challenges introduced by the WL stacking. Various device and structure solutions for the XYZ cell scaling have been suggested. The good engineering in number of electrons and cell-to-cell interference in the XYZ scaled cell will be critical in order to maintain the excellent reliability and performance of 3-D NAND.

A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances

A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation ${Z}$ -direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with 100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.

Process Development of Radical Based Dry Clean for Advanced 3D NAND Fabrication

As semiconductor device scaling marching toward sub-5 nm logic, 128+ layers 3D NAND, and advanced 1x nm DRAM technology nodes, wafer surface cleaning and residue removal in nanoscale, high aspect ratio structures become increasingly critical. Dry clean technologies are developed as alternatives for traditional wet clean applications with significant advantages in process extendibility and environmental friendliness. Furthermore, in comparison with gas only processes, radicals are considered as attractive precursors for dry clean applications due to their high reactivity en route to a high cleaning efficiency. In this work we report a novel inductively coupled remote plasma source design for radical based dry clean applications. The inductively couple plasma (ICP) source yields a high gas dissociation efficiency and a high radical density. Plasma potential and electron temperature are minimized with a unique grounded Faraday shield design and can be further suppressed with a pulsed plasma operation. Ions and electrons generated in the plasma are effectively filtered by charge separation grids, thus only leaving high flux radicals to impinge onto the wafer surface. Different radical chemistries are developed for selective removal of different dielectric, metal, and semiconductor materials, specifically for efficient cleaning inside nanoscale and high aspect ratio structures in advanced semiconductor devices. Here we report the following applications tailored toward 3D NAND manufacturing. Pre-epitaxial deposition clean in high-aspect-ratio channel holes: The requirements are to remove SiOx-like residues and damaged silicon layer at the bottom of high-aspect-ratio channel holes without damage to the exposed SiO2/SiN stacks. The aspect ratio of channel holes can exceed 50:1. A multi-step process is developed based on remote plasma chemistries containing hydrogen and fluorine radicals, in conjunction of a RF bias on wafer surface to improve directionality. SiOx-like residues of various thickness are initially completely removed at the bottom of high-aspect ratio structures. With a customized radical chemistry and a unique anisotropic process, there is no sidewall SiN/SiO2 damage and a minimal CD change. Followed by a selective removal of damaged silicon layer and surface contamination from prior etch process, a pristine and coherent surface can be prepared for the subsequent epitaxial deposition. Contact hole clean: The main objective is to remove amorphous silicon or silicon oxide interface layer at bottom of high aspect ratio contact hole structures in order to minimize metal contact resistance. The aspect ratio of contact hole structures can exceed 50:1 in advanced 3D NAND devices. Device process flow requires a high selectivity towards tungsten. A fluorine-containing remote plasma process was developed to effectively remove oxidized Si residues, create enough gouging depth, and maintain contact hole structure integrity at the same time. Contact resistance is significantly reduced with the radical based dry clean process.

Effect of SiO2 Etching Inhibitor to H3PO4 for the Selective Si3N4 Wet Etching of 3D NAND

As the number of stacked layers of the 3D NAND structure increases, the memory density of 3D NAND flash memory device increases [1]. In the fabrication of 3D NAND device, it is essential to selectively etch Si3N4 by an etchant flowing along a narrow slit followed by metal deposition. However, as the number of Si3N4/SiO2 multi-stack increases, selective etching of Si3N4 becomes difficult. In order to increase the Si3N4-to-SiO2 etch selectivity, SiO2 etching inhibitor should be added to H3PO4. Unfortunately, most of SiO2 etching inhibitors added to H3PO4 generate oxide regrowth around SiO2 layer on the Si3N4/SiO2 multi-stack structure. In this study, the mechanism of oxide regrowth occurred on the 3D NAND structure was investigated. Patterned Si3N4/SiO2 multi-stack structures were prepared. Etching experiments were performed using coupon wafers in 85% H3PO4 or etching inhibitor-added H3PO4 at 160 °C. The Si3N4 and SiO2 etching rates and Si3N4-to-SiO2 etch selectivity were measured using spectroscopic ellipsometry and oxide regrowth on the Si3N4/SiO2 multi-stack structure was analyzed using FE-SEM and HR-TEM. When the Si3N4/SiO2 multi-stack structure was etched in the SiO2 etching inhibitor-added H3PO4, oxide regrowth was observed on the SiO2 layered trenches on the Si3N4/SiO2 multi-stack structure, as shown in Fig. 1. The oxide regrowth occurred intensively at the corner of SiO2 layered trench and oxide regrowth occurred heavily at the bottom of Si3N4/SiO2 multi-stack structure as compared to the top. The overall amount of oxide regrowth on the SiO2 layered trench increased as the concentration of SiO2 etching inhibitor added to H3PO4 increased. In addition, it is shown that generation rate of etching product is an important factor to occur oxide regrowth. Based on the results, it is suggested that etching inhibitor addition and high generation rate of etching product and mass transfer limitation are responsible for the oxide regrowth. Through their optimization, selective Si3N4 etching on the Si3N4/SiO2 multi-stack structure without oxide thinning and regrowth could be obtained, as shown in Fig. 2.

Effect of SiO2 Etching Inhibitor to H3PO4 for the Selective Si3N4 Wet Etching of 3D NAND

3D NAND has a vertically stacked semiconductor structure to increase the memory density of semiconductor devices. 3D NAND devices are based on the multiply stacked silicon nitride (Si3N4) and silicon dioxide (SiO2) structure, and it is essential to high selectively etch Si3N4-to-SiO2 in the fabrication process. Hot phosphoric acid (H3PO4) has been typically used in the Si3N4-to-SiO2 selective etching process and the etch selectivity can increase by adding SiO2 etching inhibitors in H3PO4. In order to increase etching rate of Si3N4 and Si3N4-to-SiO2 etch selectivity, additives can be added in H3PO4. However, SiO2 etching inhibitors to increase Si3N4-to-SiO2 etch selectivity may occur by-product redeposition issue around the SiO2-layered trenches of Si3N4/SiO2 multi-stack structure. In this study, the etching behavior of the Si3N4/SiO2 multi-stack structures in SiO2 etching inhibitor-added H3PO4 was investigated. In addition, high selective Si3N4 etching with the control of redeposition was performed on the Si3N4/SiO2 multi-stack structure by adding proper SiO2 etching inhibitor in H3PO4.

A Study on the Diamond Wear Mechanism of Conditioner during W CMP in 3D NAND

The memory device fabrication system has already applied a lot of CMP processes for various purposes. As memory device integration increased, more CMP processes are needed. Typically CMP process can be divided into Oxide CMP, W CMP, Cu CMP, etc. These CMP technologies are important solution that can be used as memory mass production technologies develop. 3D NAND devices are being highlighted and developed as a way increase the integration method, due to the nature of its structures, 3D NAND device needs various CMP processes. In particular, the number of W CMP processes has several times multiplied over than 2D devices. In addition, more W CMP processes will be required as the device's generation evolves. However, a period of change pad, in W CMP process, is shorter than other CMP processes. Hence, it will lead to lower productivity and higher costs in fabrication system. Productivity and cost in mass production system are very important competitiveness. Thus, it is necessary to make improvements to the same level as others. There are several reasons why the W CMP process has a shorter pad replacement cycle in the 3D NAND device. One of the causes is that slurry directly or indirectly affects the wear of diamonds on conditioner. As a result, ability of polishing is decrease, pad and conditioner have no choice but to replace. In this study, we figured out which components of W slurry are being applied by W CMP in the 3D device and how they affect the wear of diamonds. And we have carried out experimental study to improve it and we will discuss the results.

Array Architectures for 3-D NAND Flash Memories

NAND Flash memories have changed and keep changing our lives. In the past two decades, NAND-based systems, in the form of Flash cards and USB keys, have replaced films and floppy disks. But disruption did not stop there. Today, NAND is really ubiquitous, as it plays the role of storage element inside smartphones and tablets; even further, it is now expanding its reach because solid-state drives (SSDs), i.e., drives built with several NAND devices, are replacing hard disk drives (HDDs) in more and more applications. To fuel this continuous evolution, NAND has to remain very aggressive in terms of cost per bit. When approaching 10-nm technologies, planar NAND is running out of steam: industry and academia have worked hard on finding a solution to this problem for more than a decade. Three-dimensional integration turned out to be the most promising alternative, and it is now eventually reaching the market. This paper is about 3-D NAND Flash memories and the related integration challenges. Charge trap and floating gate 3-D technologies will be discussed with the aid of several bird's-eye views. Advanced layout techniques will thoroughly be analyzed. Finally, future scaling trends will be presented.

Automated STEM/EDS Metrology Characterization of 3D NAND Devices

Journal Article Automated STEM/EDS Metrology Characterization of 3D NAND Devices Get access Zhenxin Zhong, Zhenxin Zhong Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Justin Roller, Justin Roller Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Oleksii Bidiuk, Oleksii Bidiuk Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Jeff Blackwood, Jeff Blackwood Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Martin Verheijen, Martin Verheijen Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Ozan Ugurlu, Ozan Ugurlu Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Jason Donald Jason Donald Materials & Structural Analysis (formerly FEI), Thermo Fisher Scientific, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124 Search for other works by this author on: Oxford Academic Google Scholar Microscopy and Microanalysis, Volume 23, Issue S1, 1 July 2017, Pages 1458–1459, https://doi.org/10.1017/S1431927617007954 Published: 04 August 2017

Silica Formation during Etching of Silicon Nitride in Phosphoric Acid

The etching of silicon nitride using phosphoric acid with silicon dioxide as a mask is an important process step used in the production of 3D NAND devices. This paper examines the theory of formation of a silica film onto the silicon dioxide surface during this etching step by performing a shell balance analysis of silica species in the etched out liquid volume of the 3D NAND structures. The method of moments is used to solve for the moments of the distribution of particle sizes, and this is used to solve for the potential energy barrier for silica particles to adhere to the silicon dioxide surface.

Modeling of Threshold Voltage Distribution in NAND Flash Memory: A Monte Carlo Method

NAND flash reliability (both endurance and retention) degrades with the scaling of NAND flash memory technology and the introduction of multilevel cell (MLC) and triple-level cell (TLC) technologies. As a result, stronger error correction code (ECC) methods are required in the solid-state drive application, especially for MLC and TLC flash memory devices. Modeling of the threshold voltage ( $V_{t}$ ) distribution in the NAND flash memory can make the ECC simulations more effective and efficient. In this paper, we show a semiphysical and Monte Carlo method to generate a reallike $V_{t}$ distribution by mimicking the NAND flash programming and data retention (DR) processes. Probability distributions used in the Monte Carlo method are obtained by the measurements of the NAND devices and data interpolation or extrapolation. Simulations by this model can obtain reallike $V_{t}$ distribution for any given Program/Erase cycle and DR time. Excellent results have been obtained and confirmed by comparing the simulations with the measured data from 16-nm NAND flash devices.