NAND Chips Research Articles

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors.

Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (Vbl) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive Vbl countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive Vbl scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.

A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm2 Bit Density

We present the industry’s first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm2, it delivers a record bit density of 23.3 Gb/mm2. Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.

Radiation-Induced Error Mitigation by Read-Retry Technique for MLC 3-D NAND Flash Memory

In this article, we have evaluated the Read-Retry (RR) functionality of the 3-D NAND chip of multilevel-cell (MLC) configuration after total ionization dose (TID) exposure. The RR function is typically offered in the high-density state-of-the-art NAND memory chips to recover data once the default memory read method fails to correct data with error correction codes (ECCs). In this work, we have applied the RR method on the irradiated 3-D NAND chip that was exposed with a Co-60 gamma-ray source for TID up to 50 krad (Si). Based on our experimental evaluation results, we have proposed an algorithm to efficiently implement the RR method to extend the radiation tolerance of the NAND memory chip. Our experimental evaluation shows that the RR method coupled with ECC can ensure data integrity of MLC 3-D NAND for TID up to 50 krad (Si).

Improving SSD Read Latency via Coding

We study the potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and NAND element failures. The NAND element failure in the present context reflects various limitations on the memory element level such as bad blocks, dies or chips that cannot be corrected by error control coding (ECC) typically employed to protect pages read off the NAND cells. Our analysis provides a clear picture of the storage-overhead and read-latency trade-offs given read failures and NAND element failures. We investigate two different ways to mitigate the effect of NAND element failures using the notion of multi-class jobs with different priorities. A strong motivation for this work is to understand the reliability requirement of NAND chip components given an additional layer of failure protection, under the latency/storage-overhead constraints.

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this article, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

Recovering multiple versions of YAFFS2 files based on Hash and timestamps

With the popularity of digital devices, digital forensic research targeted at Android-based devices has drawn increasing attention. Among the many issues in digital forensics, data recovery has received a great deal of attention. In data recovery, deleted or updated data may contain important information about past activities of the user, making such information viable evidence as far as digital forensics is concerned. In this paper, according to special characteristics of YAFFS2, we propose a new method based on the notions of Hash and timestamp to recover multiple versions of YAFFS2 files during which the relationship between timestamps and file operations is analysed. To verify the effectiveness of our proposed method, we will simulate a NAND chip under Linux and perform some experiments to show that the proposed method is both effective and efficient in the recovery of multiple versions of different types of YAFFS2 files as well as Android images.

Recovering multiple versions of YAFFS2 files based on Hash and timestamps

With the popularity of digital devices, digital forensic research targeted at Android-based devices has drawn increasing attention. Among the many issues in digital forensics, data recovery has received a great deal of attention. In data recovery, deleted or updated data may contain important information about past activities of the user, making such information viable evidence as far as digital forensics is concerned. In this paper, according to special characteristics of YAFFS2, we propose a new method based on the notions of Hash and timestamp to recover multiple versions of YAFFS2 files during which the relationship between timestamps and file operations is analysed. To verify the effectiveness of our proposed method, we will simulate a NAND chip under Linux and perform some experiments to show that the proposed method is both effective and efficient in the recovery of multiple versions of different types of YAFFS2 files as well as Android images.

Balancing Spatial Locality with Parallelism in Solid State Disks

Objectives: Modern flash memory based storage systems, such as Solid State Disks (SSDs), are actively utilizing the channel/way interleaving to exploit parallelism among multiple NAND chips. Methods/Statistical Analysis: However, the flip side of the interleaving is that it disperses data with spatial locality across different NAND blocks, which eventually causes a high garbage collection overhead. To overcome this problem, we propose a spatial locality-aware allocation policy, called SLAP. It uses the notion of stream, which is defined as a set of data having consecutive Logical Page Numbers (LPN). Findings: By allocating a stream into a NAND block separately, it can preserve the spatial locality. In addition, by handling multiple streams simultaneously, it can obtain the parallelism among NAND chips. Also, we discuss that SLAP can balance between locality-preserving and parallelism by providing a spectrum from a traditional parallelism-oriented allocation to a strict locality-preserving one. We have implemented SLAP on a page-level mapping Flash Translation Layer (FTL) that is being used as a default FTL in many commercial SSDs. Improvements/Applications: Trace-driven simulation based experimental results have shown that SLAP can improve performance by up to 35.3% with an average of 13.1%, compared with the traditional allocation policy for the three workload considered.

An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory

The read-disturb problem is emerging as one of the main reliability issues in high-density NAND flash memory. A read-disturb error, which causes data loss, occurs to a page when a large number of reads are performed to its neighboring pages. In this paper, we propose a novel integrated approach for managing the read-disturb problem. Our approach is based on our key observations from the NAND physics that the read disturbance to neighboring pages is a function of the read voltage and the read time. Since the read disturbance has an exponential dependence on the read voltage, lowering the read voltage can improve the read-disturb resistance of a NAND block. By modifying NAND chips to support multiple read modes with different read voltages, our approach allows a flash translation layer module to exploit the tradeoff between the read disturbance and write speed. Since the read disturbance is also proportional to the read time, our approach exploits the difference in the read time among different NAND pages so that frequently read pages can be less intensively read-disturbed using fast page reads. By intelligently relocating read-intensive data to read-disturb resistant blocks and pages, our approach can reduce a large portion of the time overhead from managing read-disturb errors. We also propose a proactive data migration technique which is effective in reducing large variations in I/O response times of the existing on-demand read reclaim (RR) technique. Our experimental results show that our proposed techniques can reduce the execution time overhead by 73% over the existing read-disturb management technique while reducing I/O response time fluctuations during RR activations.

Correlated Locality Data Distribution Policy for Improving Performance in SSD

In this paper, we propose in this paper present a novel locality data allocation policy as COLD(Correlated Locality Data) allocation policy. COLD is defined as a set of data that will be updated together later. By distributing a COLD into a NAND block separately, it can preserve th locality. In addition, by handling multiple COLD simultaneously, it can obtain the parallelism among NAND chips. We perform two experiment to demonstrate the effectiveness of the COLD data allocation policy. First, we implement COLD detector, and then, analyze a well-known workload. And we confirm the amount of COLD found depending on the size of data constituting the COLD. Secondly, we compared the traditional page-level mapping policy and COLD for garbage collection overhead in actual development board Cosmos OpenSSD. Experimental results have shown that COLD data allocation policy is significantly reduces the garbage collection overhead. Also, we confirmed that garbage collection overhead vary depending on the COLD size.

Volumetric density trends (TB/in.3) for storage components: TAPE, hard disk drives, NAND, and Blu-ray

Memory storage components, i.e., hard disk drives, tape cartridges, solid state drives using Flash NAND chips, and now optical cartridges using Blu-ray disks, have provided annual increases in memory capacity by decreasing the area of the memory cell associated with the technology of these components. The ability to reduce bit cell sizes is now being limited by nano-technology physics so that in order for component manufacturers to continue to increase component capacity, volumetric enhancements to the storage component are now being introduced. Volumetric enhancements include adding more tape per cartridge, more disk platters per drive, and more layers of memory cells on the silicon NAND substrate or on the optical disk substrate. This paper describes these volumetric strategies, projects density trends at the bit cell level, and projects volumetric trends at the component level in order to forecast future component capacity trends.

Flashmon V2

This paper presents Flashmon version 2, a tool for monitoring embedded Linux NAND flash memory I/O requests. It is designed for embedded boards based devices containing raw flash chips. Flashmon is a kernel module and stands for "flash monitor". It traces flash I/O by placing kernel probes at the NAND driver level. It allows tracing at runtime the 3 main flash operations: page reads/writes and block erasures. Flashmon is (1) generic as it was successfully tested on the three most widely used flash file systems that are JFFS2, UBIFS and YAFFS, and several NAND chip models. Moreover, it is (2) non intrusive, (3) has a controllable memory footprint, and (4) exhibits a low overhead (< 6%) on the traced system. Finally, it is (5) simple to integrate and used as a standalone module or as a built-in function/module in existing kernel sources. Monitoring flash memory operations allows a better understanding of existing flash management systems by studying and analyzing their behavior. Moreover it is useful in development phase for prototyping and validating new solutions.

NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD

This paper proposes a NAND controller system with a NAND channel number detector for 3D-integrated SSD. The control techniques of a program-voltage generator and an I/O frequency are proposed to enhance the SSD performance. This paper presents the solutions for the problems such as the rising time degradation and the increased power consumption caused by multi-channel parallel operation. The proposed NAND channel number detector automatically detects the number of accessed channels, that is, the number of NAND chips written at the same time. Based on the number of accessed channels, the intelligent program-voltage booster adaptively optimizes the switching clock. As a result, the proposed 3D-SSD realizes both the fastest write and the lowest energy consumption. The proposed 3D-SSD increases the write speed by 60% and decreases the energy consumption of the booster by 32%. Moreover, a dynamic I/O frequency control scheme is proposed for the future high speed I/O 3D-SSD. By selecting the adequate I/O frequencies based on the accessed number of channels, the summation of the SSD and the I/O power consumption is kept below 3.5 W even if 24 channels are operated in parallel.

Through-Silicon-Via Design with Clustering Structure and Adaptive Through-Silicon-Via Control for Three-Dimentional Solid-State-Drive Boost Converter System

This paper presents a through-silicon-via (TSV) design methodology for three-dimentional solid-state-drive (3D-SSD) system with the 20 V boost converter. Although TSV technologies give compact packaging and high performance compared to the conventional wire-bonding technology, the parasitic resistors and capacitors of TSVs may cause the performance degradation. Additionally, since the number of the activated NAND chip is dynamically changed as access patterns from real processor, the optimum design point for the boost converter is also moved according to the situation. Then, the clustering method with two different sizes of Cu-TSVs and the adaptive TSV number controlling technique for polycrystalline silicon TSVs are proposed to reduce the parasitic resistors and capacitors. With the cluster structure and Cu-TSVs, the performance of the proposed 3D-SSD is improved by ∼10%. Furthermore, the adaptive TSV number controller enhances the performance up to 2 times higher for poly-Si TSV case by reducing the parasitic elements due to TSVs.

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming

Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data retention error. The numbers of the memory cells in the higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capacitance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algorithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the asymmetric coding and the SPEA. The asymmetric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent interleaving and adaptive code selection scheme and realizes the high reliability and low power consumption.

Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.