Abstract
We present the industry’s first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm2, it delivers a record bit density of 23.3 Gb/mm2. Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.
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