N-type Metal-oxide-semiconductor Research Articles

Epitaxial growth of 4H–SiC [formula omitted] and control of MOS interface

Homoepitaxial growth on 4H–SiC (0 3 3 ̄ 8) by chemical vapor deposition (CVD) and the MOS interface have been investigated. Unintentionally-doped 4H–SiC (0 3 3 ̄ 8) epilayers showed a low background doping concentration of 3×10 14 cm −3 and a low trap concentration of 8×10 11 cm −3. Almost complete (∼100%) closing of micropipes was realized, although some of very large (>3 μm) micropipes were threading into epilayers. Conductance measurements on n-type MOS capacitors revealed that the interface state density ( D it) near the conduction-band edge is lower on 4H–SiC (0 3 3 ̄ 8) than on 4H–SiC(0 0 0 1). Higher channel mobility was obtained for inversion-type (0 3 3 ̄ 8) MOSFETs, compared to (0 0 0 1) MOSFETs.

Highly Reliable Dynamic Random Access Memory Technology for Application Specific Memory with Dual Nitrogen Concentration Gate Oxynitrides Using Selective Nitrogen Implantation

A polymetal dual gate dynamic random access memory (DRAM) for application specific memory (ASM) with dual nitrogen concentrated oxynitrides was developed for the first time. This technology uses selective nitrogen implantation performed just after gate oxidation. The nitrogen concentration of p-type metal oxide semiconductor (PMOS) in gate dielectric combined with nitrogen implantation and NO (nitric oxide) annealing is sufficiently high to suppress boron penetration, whereas that of the cell array transistor (cell-Tr) and n-type metal oxide semiconductor (NMOS) is sufficiently low to maintain the threshold voltage (Vth) without increasing the channel dosage by using only NO annealing.

High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

High performance 0.1 µm metal oxide semiconductor field effect transistors (MOSFETs) with 70 nm physical gate length and 1.7 nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ij,leak), high-speed/low-power transistors with a superior driving current are fabricated. Careful optimization of the channel, pocket and source/drain (S/D) doping profile results in a reduction of the N+/PW area junction capacitance (Cja) to 0.8 fF/µm2 and P+/NW Cja to 0.7 fF/µm2. In addition, area diode leakage current less than 50 nA/cm2 and perimeter diode leakage current less than 0.1 fA/µm are achieved. In this work, n-type MOS (NMOS) and p-type MOS (PMOS) drive current are 625 µA/µm and 285 µA/µm, respectively, at 1.0 V with an off-state current (Ioff) of 15 nA/µm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator (RO) exhibits the propagation delay time of 13 ps/stage in 1.0 V operation.

GaN MOS device using SiO2-Ga2O3 insulator grown by photoelectrochemical oxidation method

We report on a SiO/sub 2/-Ga/sub 2/O/sub 3/ gate insulator stack directly grown on n-type GaN by the photoelectrochemical oxidation method. The resultant MOS devices are fabricated using standard photolithography and liftoff techniques. The effect of annealing temperature on the SiO/sub 2/-Ga/sub 2/O/sub 3//n-type GaN MOS devices is investigated. The properties of high breakdown field, low gate leakage current, and low interface state density are investigated for the MOS devices.

Effect of laser annealing on delta-doped boron for super-steep-retrograded well formation using selective Si epitaxy

The effect of laser thermal annealing (LTA) on δ-doped B has been investigated for the applications of super-steep-retrograde (SSR) 70 nm n-type metal–oxide–semiconductor field-effect transistors using undoped selective silicon epitaxy. Shallow (⩽50 Å) melting by LTA was found to suppress the B loss, causing an anomalous lowering and fluctuation of threshold voltage (Vt), upon epitaxial channel growth and rapid thermal annealing (RTA). Under the laser fluence of 0.42 J/cm2, the B profile was also observed to freeze without further diffusion upon RTA at 900 °C for 20 s. Significant B loss observed in conventional δ-doped SSR devices stemmed from the hydrogen ambient at 800 °C required for selective silicon epitaxy as well as the rapid B outdiffusion behavior. The laser-induced surface melting decreased the outdiffusion rate by increasing the portion of substitutional B, and also led to a surface roughening which made the B loss from the silicon surface difficult. As a result of LTA, much lower Vt fluctuation with reasonable Vt was obtained along with improved short channel characteristics.

Effects of Hf contamination on the properties of silicon oxide metal–oxide–semiconductor devices

Effects of hafnium (Hf) contamination on the properties of n+-polycrystalline-Si/SiO2/Si metal–oxide–semiconductor (MOS) devices were investigated using p-type Si substrates implanted by Hf ions. Flat-band voltages (Vfb) and substrate doping concentrations (NA) of the MOS capacitors were not dependent on the Hf dose levels of 1×1011–1×1013 atoms/cm2. Leakage current density of the MOS capacitor was also not affected by the implant conditions. Electron channel mobility of n-type MOS field-effect transistors with 45-Å-thick SiO2 as gate dielectrics was not degraded by the implantation of Hf ions into the Si substrates.

The n-type metal–oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

The band-to-band tunnelling (BBT) effect in an n-type metal–oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field ET but also to the lateral electric field EL in the gate-to-drain overlap region. The main sources of these electric fields are the gate–source (Vgs) and drain–source (Vds) voltages. The modelling of the gate-induced drain leakage current, Igidl, associated with BBT remains always dependent on the drain–gate voltage, Vdg, whatever the applied values of Vgs and Vds, which cannot describe accurately the evolution of the Igidl current according to biases. Therefore, it is necessary to clarify the impact of Vgs and Vds separately. In this paper, we propose a new model of the Igidl current, which can describe the BBT effect in n-MOSFETs under various Vgs and Vds biases.

Investigation of active Si pitting and its impact on 0.15 and 0.30 μm n-type metal–oxide–semiconductor and p-type metal–oxide–semiconductor transistors

The causes of pitting on an active silicon surface and its impact on 0.15 and 0.30 μm n-type metal–oxide semiconductor (NMOS) and p-type metal–oxide–semiconductor (PMOS) transistors have been assessed. During polysilicon gate patterning, the gate oxide at the source/drain regions of the NMOS transistors may be etched away due to insufficient selectivity of the etch chemistry, improper etch chamber configuration, pattern density, and the adoption of dual-doped gate technology. The exposed silicon substrate has poor selectivity against the polysilicon gate, this causes Si pitting to occur on the source/drain active regions of the NMOS transistors. However, there is no significant pitting observed for the PMOS transistors due to the slower etch rate of the undoped polysilicon of the PMOS transistors. Pitting on the active areas severely degrades the device parameters, such as drive current, series resistance, and transconductance. This is worse for the 0.15 μm NMOS transistors compared to the 0.30 μm NMOS transistors. The channel resistance of the 0.30 μm transistors is much larger than any increase in the external resistance caused by the pitting. As a result, Si pitting has negligible effects on the device performance of long channel devices.

Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal–oxide–semiconductor transistors

Direct tunneling gate leakage current in metal–oxide–semiconductor (MOS) structures with ultrathin gate oxides is studied. The effects of inelastic scattering of inversion carriers in the gate-oxide region is taken into account in the current calculation. Open boundary conditions, incorporating the effects of wave function penetration into the gate oxide, are used to solve Schrödinger’s equation. The proposed technique, based on the Green’s function formalism, is numerically efficient and does not require determination of complex eigenenergies of a non-Hermitian matrix. Self-consistent calculations for n-type MOS devices are compared with experimental results. Excellent agreement between simulated and measured data is obtained when appropriate spatial and gate bias dependence of the inelastic scattering rate is taken into account. It is shown that due to inelastic scattering, at low gate voltages, the gate current increases significantly in devices with oxide thickness equal to 2 nm or higher. However, when the oxide thickness is reduced below 2 nm, inelastic scattering has no significant effect on gate current. The existing mismatch at lower gate voltages between experimental and modeled direct tunneling currents in devices with gate-oxide width equal to or greater than 2 nm is explained in terms of inelastic scattering effects.

Protection of MOS capacitors during anodic bonding

We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm−1 to 4 × 104 V cm−1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

Suppressed boron penetration in p+ polycrystalline-Si/Al2O3/Si metal–oxide–semiconductor structures

We demonstrate a suppressed boron penetration in p+ polycrystalline-Si (poly-Si)/Al2O3/n-Si metal–oxide–semiconductor (MOS) capacitors using a remote plasma nitridation (RPN) of Al2O3 surface. The B penetration was sufficiently suppressed for temperature to 850 °C in N2 for 30 min as manifested by the negligible flat band shift (ΔVFB) and insignificant B diffusion. The nitrogen (N) incorporation in Al2O3 surface appears to effectively impede the B diffusion into the Si channel. Increased gate leakage current for the n+ poly-Si/RPN-Al2O3/p-Si n-type MOS capacitors was observed and attributed to the reduced band gap energy of RPN-Al2O3 due to the formation of AlN and bulk defects due to RPN. Optimization of N concentration is required for the suppressed B penetration and leakage reduction.

ESD protection for the tolerant I/O circuits using PESD implantation

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μm process, this method provides a significant improvement in the cascode ESD performance.

Positron annihilation in SiO 2–Si studied by a pulsed slow positron beam

Positron and positronium (Ps) behavior in SiO 2–Si have been studied by means of positron annihilation lifetime spectroscopy (PALS) and age-momentum correlation (AMOC) spectroscopy with a pulsed slow positron beam. The PALS study of SiO 2–Si samples, which were prepared by a dry-oxygen thermal process, revealed that the positrons implanted in the Si substrate and diffused back to the interface do not contribute to the ortho-Ps long-lived component, and the lifetime spectrum of the interface has at least two components. From the AMOC study, the momentum distribution of the ortho-Ps pick-off annihilation in SiO 2, which shows broader momentum distribution than that of crystalline Si, was found to be almost the same as that of free positron annihilation in SiO 2. A varied interface model was proposed to interpret the results of the metal-oxide-semiconductor (MOS) experiments. The narrow momentum distribution found in the n-type MOS with a negative gate bias voltage could be attributed to Ps formation and rapid spin exchange in the SiO 2–Si interface. We have developed a two-dimensional positron lifetime technique, which measures annihilation time and pulse height of the scintillation gamma-ray detector for each event. Using this technique, the positronium behavior in a porous SiO 2 film, grown by a sputtering method, has been studied.

Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor

Temperature dependence of threshold voltage in n-channel SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from −150 to 150 °C and the number of the interface states present within the energy range of 0.2–0.4 eV from the conduction band edge energy Ec. This relationship revealed that the interface state profile near Ec in n-channel SiC MOSFETs can be represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility and the interface state profile also suggested that the interface states within the energy range of 0.2–0.4 eV from Ec have little influence on the channel mobility.

Influence of Interface States on High Temperature SiC Sensors and Electronics

ABSTRACTSilicon carbide based metal/oxide/semiconductor (MOS) devices are well suited for operation in chemically reactive high temperature ambients. The response of catalytic gate SiC MOS sensors to hydrogen-containing species has been assumed to be due to the formation of a dipole layer at the metal/oxide interface, which gives rise to a voltage translation of the high frequency capacitance voltage (C-V) curve. From in-situ C-V spectroscopy, performed in a controlled gaseous environment, we have discovered that high temperature (800 K) exposure to hydrogen results in (i) a flat band voltage occurring at a more negative bias than in oxygen and (ii) the transition from accumulation to inversion occurring over a relatively narrow voltage range. In oxygen, this transition is broadened indicating the creation of a large number of interface states. We interpret these results as arising from two independent phenomena – a chemically induced shift in the metal/semiconductor work function difference and the passivation/creation of charged states (DIT) at the SiO2/SiC interface. Our results are important for both chemical sensing and electronic applications. MOS capacitance gas sensors typically operate in constant capacitance mode. Since the slope of the C-V curve changes dramatically with gas exposure, we discuss how sensor-to-sensor reproducibility and device response time are influenced by the choice of operating point. For electronic applications understanding the environmentally induced changes in DIT is crucial to designing drift-free MOS devices. Our results are applicable to n-type SiC MOS devices in general, independent of the specifics of sample fabrication.

SiO2/SiC Interface Properties on Various Surface Orientations

ABSTRACTThe interface properties of MOS capacitors and MOSFETs were characterized using the (0001), (1120), and (0338) faces of 4H-SiC. (0001) and (1120) correspond to (111) and (110) in cubic structure. (0338) is semi-equivalent to (100). The interface states near the conduction band edge are discussed based on the capacitance and conductance measurements of n-type MOS capacitors at a low temperature and room temperature. The (0338) face indicated the smallest interface state density near the conduction band edge and highest channel mobility in n-channel MOSFETs among these faces.

70 nm NMOSFET Fabrication with 12 nm n+-p Junctions Using As2+ Low Energy Implantations

Nano-scale gate length metal oxide semiconductor field effect transistor (MOSFET) devices require extremely shallow source/drain extension regions with junction depth of 20–30 nm [The International Technology Roadmap for Semiconductors: Semiconductor Industry Association (1998)]. In this work, 12 nm n+-p junctions that are realized by using As2+ low energy (≤10 keV) implantation show the low sheet resistance of 1.0k Ω/□ after a rapid thermal annealing process. The As2+ implantation and RTA process make it possible to fabricate the nano-scale n-type metal oxide semiconductor field effect transistor (NMOSFET) with gate length of 70 nm. The As2+ 5 keV NMOSFET shows a small threshold voltage roll-off and a DIBL effect of 30 mV at 100 nm gate length NMOSFET devices.

Effect of oxidation method and post-oxidation annealing on interface properties of metal–oxide–semiconductor structures formed on n-type 4H-SiC C(0001̄) face

The C(0001̄) face of silicon carbide (SiC) has superior properties such as a faster oxidation ratio and a smoother surface compared with the Si(0001) face. We have investigated the oxidation and post-oxidation annealing effects on the capacitance–voltage and the interface state density (Dit) of n-type SiC metal–oxide–semiconductor (MOS) structures formed on the C(0001̄) face. It was found that pyrogenic oxidation and hydrogen annealing above 700 °C reduced Dit near the conduction-band edge. The value of Dit at Ec−E=0.2 eV is 1×1012 eV−1 cm−2, which is comparable with that of the MOS structure formed on the Si(0001) face. However, the value of Dit around the deep level at Ec−E=0.6 eV is one order of magnitude higher than that of n-type MOS structures formed on the Si(0001) face. It is very important to reduce Dit at the deep level for a high-quality SiO2/SiC interface on the 4H-SiC C(0001̄) face.

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO2/SiC interface than NO annealing time.

Reduction of interface-state density in 4H–SiC n-type metal–oxide–semiconductor structures using high-temperature hydrogen annealing

The effects of hydrogen annealing on capacitance–voltage (C–V) characteristics and interface-state density (Dit) of 4H–SiC metal–oxide–semiconductor (MOS) structures have been investigated. The Dit was reduced to as low as 1×1011 eV−1 cm−2 at Ec−E=0.6 eV using hydrogen annealing above 800 °C, where Ec−E is the energy level from the conduction-band edge. Secondary ion mass spectroscopy and Dit analysis revealed that Dit decreased with the increase of hydrogen concentration accumulated at the SiO2/4H–SiC interface. The interface states at SiO2/4H–SiC are thought to be originated from the dangling bonds of C atoms as well as Si atoms, because Dit decreases as the hydrogen annealing temperature increases and saturates around 800 °C. This high-temperature hydrogen annealing is useful for accumulation-type SiC metal–oxide–semiconductor field-effect transistors, which have n-type MOS structures to reduce the Dit.