N-type Drift Layer Research Articles

Impurity reduction in lightly doped n-type gallium nitride layer grown via halogen-free vapor-phase epitaxy

The development of gallium nitride (GaN) vertical-type metal-oxide-semiconductor field-effect transistors and p–i–n diode devices has gathered increasing attention. These devices require an n-type drift layer with a low doping level of 1016 cm−3 or less, minimized point defects inhibiting electron conduction, and a layer approximately 10 μm thick. Therefore, a practical method with a growth rate of at least several tens of μm/h and impurity concentrations of less than 1015 cm−3, except for that of dopants, is necessary. Halogen-free vapor-phase epitaxy (HF-VPE) has a high growth rate suitable for fabricating thick drift layers and utilizes a simple reaction between Ga vapor and ammonia gas (without a corrosive halogen gas), resulting in lower impurity levels. Herein, we eliminated the quartz content from the high-temperature zone to reduce the excess unintentional Si doping and identified that the nitrile gloves used for the growth preparation are other impurity contamination sources. We obtained a lightly n-type ([Si]=∼1016 cm−3) GaN layer, in which C, O, B, Fe, Mg, Al, Ca, Cr, Zn, Ni, Mn, and Ti impurity contents were below the detection limits of secondary ion mass spectrometry. Deep-level transient spectroscopy revealed that electron traps at EC − 0.26 and at EC − 0.59 eV were 2.7 × 1013 and 5.2 × 1014 cm−3, respectively. Moreover, the Hall effect analysis showed the acceptor-type defect-compensating donor content as approximately 2.7 × 1015 cm−3, resulting in a high electron mobility of HF-VPE GaN in the 30–710 K temperature range. Furthermore, we identified the Ca impurity as a deep acceptor, another killer defect leading to mobility collapse.

Correlating Structural and Electrical Characteristics of Threading Dislocations in GaN -on- Si Heterostructures and p - n Diodes by Multiple Microscopy Techniques

Structural and electrical properties of a- and a + c-type threading dislocations in metal-organic vapor-phase epitaxy-grown $\mathrm{Si}$-doped $\mathrm{Ga}\mathrm{N}$ (0001) are determined by combining multiple scanning probe microscopy approaches. The analysis examines the space-charge region (SCR) formed around dislocation cores and clarifies the role it plays in influencing the local recombination, the surface-potential characteristic, and even the conductivity. Direct evidence of the SCR is obtained from a differential capacitance (dC/dV) measurement at dislocation sites on the (0001) surface. Experimental dC/dV (V) measurement results supported by technology computer-aided design calculations of capacitance, accounting for the theoretical deep levels related to different atom-core structures of the identified dislocations, reveal quantitative differences in their respective trap densities. This study is extended to p-n $\mathrm{Ga}\mathrm{N}$ vertical diodes to analyze the doping distribution across active layers. Through a correlated cross-section investigation combining electron-channeling contrast-imaging microscopy, the underlying dislocations within the depth limited by the screening of their SCRs are found to severely impact the homogeneity of the cross-section dC/dV contrast in the low-doped n-type drift layer of the diodes. This raises serious concerns regarding any quantification efforts by differential capacitance measurements in $\mathrm{Ga}\mathrm{N}$ on $\mathrm{Si}$, where the dislocation density is in the order of ${10}^{9}\phantom{\rule{0.2em}{0ex}}{\mathrm{cm}}^{\ensuremath{-}2}$.

Freestanding High-Power GaN Multi-Fin Camel Diode Varactors for Wideband Telecom Tunable Filters

The quality, resolution, and quantity of information transmitted in RF front end modules favor compact tunable filters with varactor elements that can handle high power and that are highly linear. Gallium nitride (GaN) varactors can theoretically reach the highest quality factor figure of merit (QFOM), owing to the GaN outstanding breakdown electric field and good electron mobility. Popularly pursued GaN Schottky diode varactors suffer from leakage currents at high reverse voltage biases at their junctions and because of GaN inherent threading dislocations in thin GaN layers on foreign substrates. We devised a novel device architecture to overcome these limitations. First, we employ an interdigitated anti-series multi-Fin camel diode structure composed of a thin <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{p}^{+}$ </tex-math></inline-formula> GaN top layer situated between the Schottky metal and an n-type GaN drift layer. The anti-series symmetric Fin structure leads to excellent linearity and minimizes device parasitics to achieve measured record high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> factors. The p-GaN layer raises the barrier height to suppress reverse leakage current to maintain a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> factor at higher reverse biases than Schottky diodes. Second, we utilize GaN on Qromis Substrate Technology (QST) wafers that permit the growth of thick GaN layers with lower dislocation densities and lower leakage currents than GaN-on-Si and that are comparable to GaN-on-GaN. We report in this work the fabrication and dc, RF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}$ </tex-math></inline-formula> -parameters of these diodes, and assess their potential with empirical models. Breakdown voltage of 146 V and extrapolated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> factor of 84, 33, and 9 at 2, 5, and 18 GHz, respectively, are obtained in multi-Fin back-to-back varactor device configuration.

Fabrication of Ga2O3 Schottky Barrier Diode and Heterojunction Diode by MOCVD.

In this article, we reported on a Ga2O3-based Schottky barrier diode and heterojunction diode from MOCVD. The Si-doped n-type Ga2O3 drift layer, grown by MOCVD, exhibited high crystal quality, flat surfaces, and uniform doping. The distribution of unintentional impurities in the films was studied. Then nickel Schottky barrier diode and p-NiO/n-Ga2O3 heterojunction diode were fabricated and measured. Without any electric field management structure, the Schottky barrier diode and heterojunction diode have specific resistances of 3.0 mΩ·cm2 and 6.2 mΩ·cm2, breakdown voltages of 380 V and 740 V, thus yielding power figures of merit of 48 MW·cm-2 and 88 MW·cm-2, respectively. Besides, both devices exhibit a current on/off ratio of more than 1010. This shows the prospect of MOCVD in power device manufacture.

Normally-off β-Ga2O3 MOSFET with an Epitaxial Drift Layer.

A normally-off β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed using a technology computer-aided design (TCAD) device simulation, which employs an epitaxial drift layer grown on an n-type low-doped body layer. The low-doped body layer under the MOS gate enabled normally-off operation, whereas the epitaxial drift layer determined the on-resistance and breakdown characteristics. The effects of the doping concentration of each layer and thickness of the drift channel layer on the device characteristics were investigated to design a device with a breakdown voltage of 1 kV. A threshold voltage of 1.5 V and a breakdown voltage of 1 kV were achieved by an n-type body layer with a doping concentration of 1 × 1015 cm−3 and an n-type drift layer with a doping concentration of 3 × 1017 cm−3, a thickness of 150 nm, and a gate-to-drain distance of 9.5 μm; resulting in an on-resistance of 25 mΩ·cm2.

Vertical GaN p+-n junction diode with ideal avalanche capability grown by halide vapor phase epitaxy

A vertical GaN p+-n junction diode with an ideal breakdown voltage was grown by halide vapor phase epitaxy (HVPE). A steep p+-n interface was observed even with the use of the HVPE method. No Si-accumulating layer was formed at the p+-n interface because of the continuous HVPE growth from the n-type drift layer to the p-type layer. This method provides improved electrical properties compared with the regrowth of p-type GaN layers. The minimum ideality factor of approximately 1.6 was obtained. The breakdown voltage increased from 874 to 974 V with the increase in the temperature from 25 to 200 °C, which suggests that avalanche multiplication causes the breakdown. The temperature-dependent breakdown voltage was in good agreement with the breakdown voltage calculated using the ideal critical electric field. These results indicate that HVPE is promising for the fabrication of vertical GaN power devices.

(Invited) MOCVD GaN-on-GaN Towards Vertical Power Devices & MOCVD Development of β-Ga2O3

Gallium nitride (GaN) has been considered as a promising candidate for power device applications due to the wide band gap (3.4 eV), high critical electric field (3 MV/cm) and high electron mobility (>1000 cm2/Vs). Baliga’s figure of merit (BFOM) of GaN is more than 500 times higher than silicon (Si) and more than three time higher than silicon carbide (SiC). Due to the availability of native GaN substrates, it is feasible to develop high performance GaN vertical power devices on low-defect GaN substrate. GaN-on-GaN vertical PN diode with record high VBR ~5 KV was reported [1], presenting the potential of GaN as a high-performance material for power devices. Compared with SiC, the performance of GaN vertical PN diodes is still limited by its high background doping in n-type drift layer at mid-1015 to low-1016 cm-3 range. Therefore, it is of great importance to study the sources and incorporation mechanisms of unintentionally doped background impurities in metal-organic chemical vapor deposition (MOCVD) GaN growth, to control the impurity incorporation, in order to maximize device performance for GaN based vertical power devices. This talk will discuss the dependence of MOCVD growth conditions on the impurity incorporations such as C, Si, O, H, and Fe. Quantitative SIMS and CV measurements are used for material characterization.Ultrawide bandgap (UWBG) gallium oxide (Ga2O3) with a band gap of 4.5-4.9 eV, represents an emerging semiconductor material with excellent chemical and thermal stability. The monoclinic β-phase Ga2O3 represents the thermodynamically stable crystal among the known five known phases (α, β, γ, d , ε). The breakdown field of β-Ga2O3 is estimated to be 6-8 MV/cm. These unique properties make β-Ga2O3 a promising candidate for high power electronic device and solar blind photodetector applications. Single crystal β-Ga2O3 substrates can be synthesized by scalable and low cost melting based growth techniques. MOCVD growth technique was used to develop high quality β-Ga2O3 thin films and its ternary alloy (AlxGa1-x)2O3. Control of background and n-type doping in β-Ga2O3 will be discussed. Record carrier mobilities of 194 cm2/V·s at room temperature and ~10,000 cm2/V·s at low temperature were measured for MOCVD β-Ga2O3 thin films [2]. MOCVD growth of β-AlGaO targeting for Al composition of > 40% will be discussed [3, 4]. Acknowledgement: The authors acknowledge the funding support from Advanced Research Projects Agency-Energy (ARPA-E) DE-AR0001036, U.S. Department of Energy's Office of Energy Efficiency and Renewable Energy (EERE) under the Advanced Manufacturing Office, FY18/FY19 Lab Call, the Air Force Office of Scientific Research FA9550-18-1-0479 (AFOSR, Dr. Ali Sayir) and the National Science Foundation (1810041, 1755479). [1] H. Ohta, N. Asai, F. Horikiri, Y. Narita, T. Yoshida, and T. Mishima, Jpn. J. Appl. Phys. 58, SCCD03 (2019).[2] Z. Feng, A F M A. U. Bhuiyan, M. R. Karim, H. Zhao, Appl. Phys. Letts., 114, 250601, 2019.[3] A F M A. U. Bhuiyan, Z. Feng, J. M. Johnson, Z. Chen, H. -L. Huang, J. Hwang, H. Zhao, Appl. Phys. Lett., 115, 120602, 2019.[4] A F M A. U. Bhuiyan, Z. Feng, J. M. Johnson, H.-L. Huang, J. Sarker, M. Zhu, M. R. Karim, B. Mazumder, J. Hwang, and H. Zhao, APL Materials, 8, 031104, 2020.

Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers

Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.

AlInN/GaN diodes for power electronic devices

AlInN/GaN power diodes consisting of a p-type GaN and a 300 nm thick n-type AlInN drift layer are demonstrated. The p–n junction is grown using metalorganic chemical vapor deposition, and the AlxIn1−xN drift layer is lattice-matched to GaN (x ∼ 0.82) with an electron concentration of ∼8 × 1016 cm−3 after correcting for the 2-dimensional electron gas. The diodes exhibit ∼−60 V blocking capability. Under forward bias, the diode has a turn-on voltage of ∼4 V. If experimental challenges are overcome, the ultrawide bandgap and high mobility of an AlInN drift layer could increase the performance of GaN-based power devices.

Change of high-voltage conduction mechanism in vertical GaN–on–GaN Schottky diodes at elevated temperatures

Current-voltage-temperature characteristics (0 °C to 150 °C) of SBDs on highly compensated 15 μm and 30 μm n-type GaN drift layer were measured for voltages up to −300 V and up to −800 V, respectively. When the temperature is between 75 °C and 100 °C, both SBDs exhibited a similar change in conduction mechanism from thermionic field emission (TFE) to thermionic emission (TE) due to the activation of N-vacancies (VN) (Ea = −1.67 ± 0.02 eV). However, at high voltages when the temperature is >100 °C, the conduction mechanism changes from TE to TFE due to the de-trapping of electrons from activated carbon-traps (Ea = +0.69 eV) in the grown drift layers.

(Invited) Selective Area Growth of p-Type GaN for Gallium Nitride Power Switching Transistors

Superior electronic material properties of GaN semiconductors compared to Si will enable the foundational diodes and transistors for the next revolution in power management technology. To date, high-performance GaN diodes have been demonstrated with breakdown voltages near 5 kV and specific on-resistances of less than 5 mΩ-cm2 [1]. However, a viable GaN vertical power switching transistor is the missing element necessary to realize advanced power management systems utilizing GaN. While GaN transistors are now ubiquitous in RF systems, their lateral device architecture inherently limits these devices to niche applications in power systems. Rather, high-voltage systems rely on vertical device architectures where current flow is normal to the semiconductor surface. Vertical power electronics devices such as junction field effect transistors (JFETs) require selective areas of p-type semiconductor surrounded by lightly-doped n-type semiconductor. For Si power devices, p-type regions are implanted in n-type drift regions to create p/n junctions that act as a gate and pinch-off current. Ion implantation presents challenges in GaN and requires specialized equipment and processes, including high-pressure and high-temperature annealing, for dopant activation [2]. Our previous work using metal-organic chemical vapor deposition (MOCVD) where p-type GaN was regrown on a lightly-doped, non-etched n-type drift layer demonstrated planar p/n diodes with the same electrical performance as continuously-grown devices. However, when dry-etching processes are used before the regrowth of the p-type GaN layer, as would be needed to define a regrown area, planar diodes demonstrate higher forward and reverse leakage currents, and lower breakdown voltage. Deep Level Optical Spectroscopy (DLOS) was used to identify the source of the higher forward and reverse leakage currents observed in diodes with p-type anodes re-grown on inductively coupled plasma (ICP) dry-etched n-type drift layers. We will report DLOS studies of various diode structures that show the formation of a mid-gap trap located ~ 1.7 eV below the conduction band in dry-etched, lightly doped (Nd-Na = 2x1016 cm-3) drift layers. We also will show that various wet-chemical treatments of the dry-etched n-type drift layer prior to p-anode regrowth results in diodes with 1 to 2 orders of magnitude lower reverse leakage current. DLOS measurements of regrown diodes showed a 3 times reduction in the density of the mid-gap deep level trap following wet-chemical treatment. These studies establish the connection between high reverse and forward leakage currents with residual damage caused by dry-etching and that this damage can be mitigated by with wet-chemical treatments prior to regrowth of the p-anode. The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency – Energy (ARPA-E), U.S. Department of Energy under the PNDIODES programs directed by Dr. Isik Kizilyalli. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. H. Ohta et al., J. J. Appl. Phys., 57, 04FG09 (2018).T.J. Anderson et al., Elec. Lett., 50(3), 197 (2014).

15 kV n-GTOs in 4H-SiC

High performance 15 kV n-GTOs were demonstrated for the first time in 4H-SiC. The device utilized a 140 μm thick, lightly doped n-type drift layer, with 1450°C lifetime enhancement oxidation, which resulted in a carrier lifetime of 17.5 μs. The p+ backside injector layer was thinned to minimize parasitic resistances. A room temperature forward voltage drop of 5.18 V was observed at a current density of 100A/cm2. A 1 cm2 device showed a leakage current of 0.17 μA at 15 kV. The 4H-SiC n-GTO showed latching characteristics, and showed a turn-off time of 170 ns in a resistive load switching setup, which represents about a factor of 45 improvement in turn-off speed over 4H-SiC p-GTOs with comparable voltage and current ratings.

Direct evidence of Mg diffusion through threading mixed dislocations in GaN p–n diodes and its effect on reverse leakage current

Mg diffusion is a common problem in GaN devices with p–n junctions. Although this impurity diffusion is reported to occur through threading dislocations (TDs), no direct evidence has yet been obtained. Therefore, we tried the direct observation of Mg diffusion by atom probe tomography (APT) analysis. The n-type drift layer of the fabricated p–n diode was exposed, and etch pits were formed on the drift layer to identify the TD position. The APT analysis around TDs was carried out by lifting out the drift layer around specific etch pits using a focused ion beam to include TDs. The relationship between the etch pit shape and the TD type was confirmed by cross-sectional scanning transmission electron microscopy observation. The APT analysis of two types of etch pits formed on the mixed dislocations was performed, and Mg diffusion was clearly observed through the mixed dislocations. In this work, we show direct evidence of Mg diffusion via mixed dislocations in GaN p–n diodes and its effect on reverse leakage current.

Regrown Vertical GaN p–n Diodes with Low Reverse Leakage Current

Vertical c-plane GaN p–n diodes, where the p-GaN layer is formed by epitaxial regrowth using metal–organic chemical-vapor deposition, are reported. Current–voltage (I–V) performance similar to continuously grown p–n diodes is demonstrated, including low reverse leakage current and reverse breakdown voltage in excess of −600 V, despite the lack of field management structures to increase the reverse breakdown voltage. Secondary-ion mass spectrometry analysis of regrown interfaces reveals that the primary source of Si at the regrown interface (“Si spike”) is ex situ contamination during wafer handling prior to loading for regrowth. Continuously grown p–n diodes with intentional Si doping at the p–n junction do not show degraded I–V performance for Si sheet concentrations < 8 × 1011 cm−2. Regrown diodes where the n-type drift layer is (plasma) dry-etched before p-GaN regrowth demonstrate significantly higher reverse leakage current. From these results, we conclude that the presence of Si < 8 × 1011 cm−2 and the epitaxial regrowth process are not responsible for performance degradation. Removal of dry-etch-induced current leakage mechanisms, prior to epitaxial regrowth, should enable a method for selective-area p-type doping control that could lead to realization of high-performance vertical power transistors.

Implementation of a 900 V Switching Circuit for High Breakdown Voltage β-Ga2O3 Schottky Diodes

This paper presents a switching circuit for high breakdown-voltage Ga2O3 vertical Schottky rectifiers. Field-plated edge-terminated (FPET) vertical Schottky diodes were fabricated on a 20-μm thick Si-doped n-type Ga2O3 drift layer which was grown on the 650-μm thick β-Ga2O3 substrate via halide vapor phase epitaxy (HVPE). The measured reverse recovery time of the proposed Ga2O3 Schottky diode was 81 ns when switched to a reverse bias voltage of −900 V. The implementation of a switching circuit with the novel Ga2O3 diode is the first demonstrated at such a high switching voltage. This paper also provides insights for the practical implementation of the Ga2O3 vertical Schottky rectifiers from device fabrication to circuit design.

(Invited) Material Advances Toward Vertically-Conducting AlGaN Power Transistors

Due to their large bandgaps (≥ 3.4 eV) compared to Si and SiC, AlGaN alloys have superior material properties that are appealing for the next generation of high-voltage power devices. Most notable is that the critical electrical field scales as the bandgap to the 2.0-2.5 power. Thus, diodes employing wide bandgap semiconductors are expected to operate at higher breakdown voltages with thinner and more heavily-doped drift regions, leading to lower resistive losses compared to Si-based devices. Additionally, the formation of AlGaN-based heterojunctions and the utilization of polarization fields offer design options not possible for devices based on materials such as SiC and diamond. Noteworthy demonstrations of high voltage (> 3 kV) PN and Schottky barrier diodes in both GaN and AlGaN alloys confirm the potential of III-Nitride materials for power devices. However, full exploitation of the efficiency gains promised by III-Nitrides for power management systems also requires vertically-conducting transistors for current switching, in addition to diodes. Analogous to power diodes, vertically-conducting power transistors such as D-MOSFETs employ a thick n-type drift layer to stand-off high reverse voltage, but unlike simple PN diodes, have the p-type material limited to spatially defined regions over the surface of the device. “Selective area p-doping” is typically accomplished in SiC and Si devices by implantation and activation of p-type dopants. However, implantation processing in III-Nitride structures has to date only yielded PN junctions that exhibit significantly higher reverse current leakage than continuously-grown PN junctions. Selective-area epitaxial regrowth of p-type material in regions etched into the drift layer offers an alternative to implantation. However, regrown pn junctions on plasma-etched III-Nitrides with low reverse leakage current have not been demonstrated. In this presentation we will discuss the advances in epitaxial p-regrowth for forming pn junctions on inductively-coupled plasma (ICP) etched n-type GaN and Al0.3Ga0.7N drift layers. The role and sources of unintentionally-introduced Si at the regrown interface will be presented. Additionally, approaches to ameliorate damage and defect states introduced by ICP etching through wet-chemical and in-situ reactor thermal treatments prior to p-regrowth will be related to current-voltage characteristics of regrown diodes. While high voltage GaN-based diodes have been fabricated on vertically-conducting GaN substrates, AlGaN-based high voltage diodes with thick drift layers (≥ 5 μm) have been fabricated on AlN and sapphire substrates. The insulating nature of these substrates necessitates planar device geometries that result in high ohmic losses, heating, and degraded device performance. However, the thick drift layer and the smaller lattice constant of AlGaN alloys present significant challenges for realizing vertically-conducting AlGaN power devices on GaN substrates. Here we report a method for fabricating vertically-conducting AlxGa1-xN PN junctions grown on conducting GaN substrates. An n-type GaN substrate is patterned with parallel, sub-micron-wide mesas separated by trenches etched > 0.5 μm deep prior to AlxGa1-xN overgrowth using metal-organic vapor phase epitaxy. We find that growth temperature, V/III ratio, and group-III molar flux can be used to manipulate the crystalline facets formed along the etched pattern prior to AlxGa1-xN coalescence. Using the described process, coalesced planar AlxGa1-xN epitaxial layers were achieved with less than 6 μm of overgrowth for Al mole fractions up to 0.45, which is the highest Al mole fraction reported to date. Cathodoluminescence measurements of an overgrown Al0.3Ga0.7N epilayer indicate that the density of threading dislocations is mid x 108 cm-2 which is similar to that measured for Al0.3Ga0.7N epilayers overgrown on patterned Al0.3Ga0.7N on sapphire. The current-voltage characteristics of vertically-conducting AlGaN PN diodes grown on GaN substrates will be presented. The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency – Energy (ARPA-E), U.S. Department of Energy under the PNDIODES program managed by Dr. Isik Kizilyalli. This work was also supported, in part, by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525

Suppression of Punch-Through Current in 3 kV 4H-SiC Reverse-Blocking MOSFET by Using Highly Doped Drift Layer

Low on-resistance 4H-SiC reverse-blocking (RB) metal–oxide–semiconductor field-effect transistors (MOSFETs) have been developed by adopting a non-punch-through (NPT) drift layer in order to suppress the punch-through (PT) current under the reverse-blocking condition. The n-type NPT drift layer was 40- ${\mu }\text{m}$ thick doped to $3.7\times 10^{15} $ cm−3. The forward and reverse breakdown voltages of the fabricated NPT RB MOSFET were 3.6 kV and −3.0 kV, respectively. The differential specific on-resistance was 13.5 $\text{m}\Omega \cdot $ cm2 at room temperature, which was 33% lower than that of a 3 kV PT RB MOSFET, demonstrating superiority of the developed NPT RB MOSFET as a high-performance bidirectional switch.

Fabrications and characterizations of high performance 1.2 kV, 3.3 kV, and 5.0 kV class 4H–SiC power SBDs**Project supported by the National Natural Science Foundation of China (Grant Nos. 61404098, 61176070, and 61274079), the Doctoral Fund of Ministry of Education of China (Grant Nos. 20110203110010 and 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), and the Key

In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H–SiC power Schottky barrier diodes (SBDs) are fabricated with three N-type drift layer thickness values of 10 μm, 30 μm, and 50 μm, respectively. The avalanche breakdown capabilities, static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical predictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H–SiC theoretical limit line. The best achieved breakdown voltages (BVs) of the diodes on the 10 μm, 30 μm, and 50 μm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances (Ron−sp) are 2.1 mΩ ·cm2, 7.34 mΩ·cm2, and 30.3 mΩ·cm2, respectively.

Vertical GaN Power Diodes With a Bilayer Edge Termination

Vertical GaN power diodes with a bilayer edge termination (ET) are demonstrated. The GaN p-n junction is formed on a low threading dislocation defect density ( $10^{4}-10^{5}$ cm $^{-2}$ ) GaN substrate, and has a 15- $\mu \text{m}$ -thick n-type drift layer with a free carrier concentration of $5\times 10^{15}$ cm $^{-3}$ . The ET structure is formed by $N$ implantation into the p+-GaN epilayer just outside the p-type contact to create compensating defects. The implant defect profile may be approximated by a bilayer structure consisting of a fully compensated layer near the surface, followed by a 90% compensated (p) layer near the n-type drift region. These devices exhibit avalanche breakdown as high as 2.6 kV at room temperature. Simulations show that the ET created by implantation is an effective way to laterally distribute the electric field over a large area. This increases the voltage at which impact ionization occurs and leads to the observed higher breakdown voltages.

Experimental Study of Counter-Doped Junction Termination Extension for 4H–SiC Power Devices

In this letter, a counter-doped junction termination extension (CD-JTE) structure was experimentally implemented and studied. Two groups of 4H-SiC PiN diodes were fabricated with two n-type drift layer thicknesses of 11 and 30 μm, respectively, and with different termination structures, in order to demonstrate the wide JTE dose tolerance of CD-JTE. Three different doses, 1.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> , 2.2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> , and 2.8×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , were used for the critical JTE implantation. The measured breakdown voltages (BVs) of the diodes with all termination structures and JTE doses were compared with simulation predictions. Electroluminescence at the BV was recorded and used to locate the peak electrical field. The test results matched well with the simulation results. As a result of the effectiveness and robustness of the CD-JTE, the best achieved BVs from the diodes on the 11and 30-μm epilayers were 1850 and 4800 V, respectively.