Vertical GaN Power Diodes With a Bilayer Edge Termination

Abstract

Vertical GaN power diodes with a bilayer edge termination (ET) are demonstrated. The GaN p-n junction is formed on a low threading dislocation defect density ( $10^{4}-10^{5}$ cm $^{-2}$ ) GaN substrate, and has a 15- $\mu \text{m}$ -thick n-type drift layer with a free carrier concentration of $5\times 10^{15}$ cm $^{-3}$ . The ET structure is formed by $N$ implantation into the p+-GaN epilayer just outside the p-type contact to create compensating defects. The implant defect profile may be approximated by a bilayer structure consisting of a fully compensated layer near the surface, followed by a 90% compensated (p) layer near the n-type drift region. These devices exhibit avalanche breakdown as high as 2.6 kV at room temperature. Simulations show that the ET created by implantation is an effective way to laterally distribute the electric field over a large area. This increases the voltage at which impact ionization occurs and leads to the observed higher breakdown voltages.