N-type Czochralski Silicon Wafers Research Articles

Characterisation of striations in n-type silicon wafer processed with polysilicon contacts

We analysed the electronic and optical properties of oxygen-related striations in n-type Czochralski silicon wafers that underwent polysilicon contact process using deep level transient spectroscopy and micro-photoluminescence. Band to band micro-photoluminescence spectra measured at low temperature (80 K) indicate that the dark striations with low lifetime originate from nano-scale oxygen precipitates. Deep level transient spectroscopy results indicate that such nano-scale precipitates cannot be considered as point defects and analysed with Shockley-Read-Hall recombination statistics, but must be treated as extended defects with a continuous spectrum of energies.

Deep Level Assessment of n-Type Si/SiO2 Metal-Oxide-Semiconductor Capacitors with Embedded Ge Quantum Dots

Device structures with silicon or germanium nanodots embedded in an oxide matrix may find application in the field of Non-Volatile Memories (NVMs) [1,2] or photonics [3,4]. In the former case, the nanodots can become charged by tunneling of electrons or holes from the silicon substrate through a tunnel oxide. Successful operation requires that the charge does not leak away by the assistance of traps or defects in the material stack. The latter can be probed by techniques like Admittance Spectroscopy [5] or Deep-Level Transient Spectroscopy (DLTS) [2,5]. In the present work we report on a systematic investigation of Metal-Oxide-Semiconductor (MOS) capacitors fabricated on n-type Czochralski silicon substrates and containing Ge nanodots with different size. Ge nanodots with average diameter of 1, 2 or 3 nm have been deposited by Molecular Beam Epitaxy (MBE) on a 5 nm tunnel oxide, thermally grown on n-type Czochralski silicon wafers. An Atomic Force Microscopy (AFM) picture is shown in Fig. 1. Next, 50 nm of SiO2 is deposited. MOS capacitors are prepared by thermal evaporation of 2 mm diameter Al gate contacts, while InGa+In foil ohmic contacts are prepared on the silicon substrate side. The device structure is schematically shown in Fig. 2. Capacitance-Voltage (C-V) characterization is performed at a fixed frequency f=1 MHz, using both a forward and reverse gate voltage sweep. As can be seen in Fig. 3, the presence of the Ge nanodots has a pronounced impact on the C-V characteristics: there is a shift towards positive flat-band voltage, compared with the zero dot reference, a strong increase of the accumulation capacitance and, for the nanodot samples, the hysteresis increases with the increase in nanodot size. For temperature (T-) scan DLTS, the capacitors are mounted in a helium contact gas cryostat cooled with liquid nitrogen. Measurements at different bias pulses from reverse bias (VR) to the pulse bias (VP) are performed in parallel in order to probe the electron traps in different parts of the structure. An example is given in Fig. 4, for the 1 nm nanodots sample. It shows that in deep depletion, there is a broad peak between 150-250 K which could stem from the response of filled interface traps. The increase found at room temperature may originate from minority carrier generation in the depletion region [2,5,6]. When probing closer to the interface, for more positive VR, a pronounced but broad peak around 200 K dominates the spectra. From the Arrhenius plot shown in Fig. 5, it is concluded that it corresponds to the dangling bond (Pb) acceptor level at about 0.31 eV from the conduction band [2,5,6]. Maximum densities are estimated in the range of 5x1011 cm-2eV-1. A comparison of the spectra near the interface for the different samples studied is provided in Fig. 6 and will be discussed in more detail in the conference paper.

Oxygen-related defects in n-type Czochralski silicon wafers studied by hyperspectral photoluminescence imaging

Oxygen-related Thermal Donors in n-type Czochralski silicon (Cz-Si) wafers have been investigated using hyperspectral photoluminescence imaging and OxyMap. Thermal Donors give rise to two photoluminescence emissions, one narrow peak at 0.767 eV, and one broad band with centre peak at 0.72 eV that is also measurable at room temperature. The spectral imaging was first carried out on the sample cooled to 90 K, then repeated at room temperature (300 K). The possibility to delimitate at room temperature defects-rich zones with hyperspectral photoluminescence imaging is evidenced.

Bulk defect formation under light soaking in seed-end n-type Czochralski silicon wafers – Effect on silicon heterojunction solar cells

We report on a degradation of the electronic properties of uncompensated seed-end n-type (phosphorus-doped) Czochralski silicon wafers under light soaking. We unambiguously demonstrate that this degradation is related to the formation and/or activation of a bulk defect under illumination. We bring general information about its activation/formation (illumination intensities, spatial distribution) as well as deactivation features. We show that this defect can be permanently suppressed in a few seconds at high temperatures (850°C). Conversely annealing at low temperature (200°C) was found to lead only to a temporary deactivation, the defect being reactivated/reformed after subsequent illumination. As a consequence, this defect could be harmful to solar cell technologies processed at low temperature, such as amorphous/crystalline silicon heterojunction (SHJ). The impact of the defect on SHJ cells performances is experimentally assessed at device level. Eventually the possible nature of the defect is discussed in the light of all collected data.

Upgraded metallurgical-grade silicon solar cells with efficiency above 20%

We present solar cells fabricated with n-type Czochralski–silicon wafers grown with strongly compensated 100% upgraded metallurgical-grade feedstock, with efficiencies above 20%. The cells have a passivated boron-diffused front surface, and a rear locally phosphorus-diffused structure fabricated using an etch-back process. The local heavy phosphorus diffusion on the rear helps to maintain a high bulk lifetime in the substrates via phosphorus gettering, whilst also reducing recombination under the rear-side metal contacts. The independently measured results yield a peak efficiency of 20.9% for the best upgraded metallurgical-grade silicon cell and 21.9% for a control device made with electronic-grade float-zone silicon. The presence of boron-oxygen related defects in the cells is also investigated, and we confirm that these defects can be partially deactivated permanently by annealing under illumination.

>23% High-Efficiency Tunnel Oxide Junction Bifacial Solar Cell With Electroplated Cu Gridlines

Based on the metal-insulator-semiconductor concept, Triex cell is a proprietary device structure that combines a tunnel oxide junction with doped a-Si thin-film emitter layers on n-type Czochralski silicon wafers. A simple patterning process is used along with cost-effective copper electrochemical plating to form the electrodes. This paper reports a >23% high-efficiency Triex solar cell, postoptimizing key process areas to improve passivation, junction quality, and shading effects. High open-circuit voltage (V oc ) of 739 mV and good fill factor of 80.5% have been demonstrated on a 6-in solar cell. A champion 380-W Triex bifacial module is also validated under standard test conditions.

Excellent passivation of thin silicon wafers by HF-free hydrogen plasma etching using an industrial ICPECVD tool

In this work, hydrogen plasma etching of surface oxides was successfully accomplished on thin (∼100 µm) planar n-type Czochralski silicon wafers prior to intrinsic hydrogenated amorphous silicon [a-Si:H(i)] deposition for heterojunction solar cells, using an industrial inductively coupled plasma-enhanced chemical vapour deposition (ICPECVD) platform. The plasma etching process is intended as a dry alternative to the conventional wet-chemical hydrofluoric acid (HF) dip for solar cell processing. After symmetrical deposition of an a-Si:H(i) passivation layer, high effective carrier lifetimes of up to 3.7 ms are obtained, which are equivalent to effective surface recombination velocities of 1.3 cm s–1 and an implied open-circuit voltage (Voc) of 741 mV. The passivation quality is excellent and comparable to other high quality a-Si:H(i) passivation. High-resolution transmission electron microscopy shows evidence of plasma-silicon interactions and a sub-nanometre interfacial layer. Using electron energy-loss spectroscopy, this layer is further investigated and confirmed to be hydrogenated suboxide layers. (© 2015 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

(Invited) The Impact of Oxide Precipitates on Minority Carrier Lifetime in Czochralski Silicon

Oxide precipitates form in silicon for microelectronic and photovoltaic applications, and act as strong recombination centres. We have measured the injection-dependence of minority carrier lifetime in ~50 samples from p-type and n-type Czochralski silicon wafers with a wide range of precipitate densities. We find that all the data can be parameterized in terms of two independent Shockley-Read-Hall centres. The first is at EV + 0.22eV, and has a capture coefficient for electrons 157 greater than that for holes. The second is at EC - 0.08eV and has a capture coefficient for holes ~1,200 greater than that for electrons. The density of the centres is approximately dependent on the precipitate concentration. The existence of dislocations and stacking faults around the precipitates increases the density of both centres.

High Efficiency n-Type Metal Wrap through Cells and Modules

This paper describes results of metal wrap through (MWT) cells produced from n-type Czochralski silicon wafers, and modules produced from those cells. The use of n-type silicon as base material allows for high efficiencies: for front emitter contacted industrial cells, efficiencies upto nearly 20% have been reported. MWT cells allow even higher cell efficiency, and additionally full back-contacting of the MWT cells in a module results in reduced cell to module (CTM) losses.MWT cells were produced by industrial process technologies. The efficiency of the MWT cells reproducibly exceeds the front contact cells based on the same technology by about 0.2-0.3%, and routes for further improvement are analysed.60-cell modules were produced from both types of cells. The MWT module, based on integrated backfoil, produced 3% higher power output than the comparable tabbed front emitter contact module. In particular differences in CTM loss of current and fill factor will be presented. CTM current differences arise from the higher packing density, and lower reflectance of the backfoil, in MWT modules. CTM FF differences are related to resistive losses in copper circuitry on the backfoil versus tabs. The CTM FF loss of the MWT module was 2.2%abs lower than for the tabbed front emitter contact module. Also here the losses are analysed and routes for improvement discussed.

A chromium-free etchant for delineation of defects in heavily doped n-type silicon wafers

Delineation of defects in the heavily doped n-type Czochralski silicon wafers by preferential etching is an issue not having been essentially solved. Herein, a chromium-free etchant based on HNO 3–HF–H 2O system, with an optimum volume ratio of V HNO 3 % : V HF % : V H 2 O % = 20 % : 45 % : 35 % , has been developed. It can reveal well the defects such as dislocation and oxygen precipitation-induced bulk microdefects (BMDs) in the heavily doped n-type silicon wafers with resistivities even lower than 1 mΩ cm. Moreover, this etchant is appropriate to delineate the defects on (1 1 1), (1 1 0) or (1 0 0) surface of silicon crystal. Furthermore, the density of oxygen precipitation-induced BMDs in the heavily doped n-type silicon wafers derived from the preferential etching using this newly developed etchant correlates well with that derived from scanning infrared microscopy (SIRM) within its detection limit.

Resistivity of linear scratches in doped (100) n-type single-crystal silicon

Four-point probe measurements have been made on (100) n-type Czochralski silicon wafers of initial resistivities 0.016, 0.96, and 3.35 Ω cm. The probe tips straddled linear single scratches formed by a Vickers pyramid diamond. The diamond was dead-loaded with 0.25 N, and the scratches were made in a laboratory air environment with a relative humidity of 50%, as the silicon wafer was held at various elevated temperatures. The measurements show that the relative change in resistivity increases with temperature up to an optimum temperature, after which the resistivity decreases. The temperature at which the maximum occurs and at which the relative change in resistivity occurs depends on the initial resistivity of the wafers; the temperature at which the maximum change in relative resistivity occurs is 200 °C for the 0.016- and 0.96-Ω cm wafers and 250 °C for the 3.35-Ω cm wafer. The relative change between the undamaged wafer resistivity and the resistivity including the scratches for these same samples was 4%, 7%, and 9%. Scanning electron micrographs of the scratches showed that the scratch morphology also depended on the temperature; as the temperature is increased, the grooves become shallow and display evidence of ploughing. An analysis of the four-point probe geometry shows that the voltage in the four-point probe measurement depends on the size and the conductivity of the damage surrounding the scratches.

Fixed pattern noise in the solid-state imagers due to the striations in Czochralski silicon crystals

The concentric circle pattern of growth striations in Czochralski (CZ) silicon wafer has been found to cause the fixed pattern noise in the reproduced image by solid-state imagers with the p-well structure. The microgrowth striations of dopant impurities in 4-in. n-type CZ silicon wafers have been examined in terms of noise video signals of p-well Charge Priming Device imagers. Striation periods as narrow as 10 μm can be revealed, which may be overlooked by the conventional spreading resistance method.