N-type 4H-SiC Epilayers Research Articles

Impact of carbon injection in 4H-SiC on defect formation and minority carrier lifetime

Point defects in silicon carbide (SiC) can act as charge carrier traps and have a pronounced impact on material properties such as the mobility and carrier lifetime. Prominent among these traps is the carbon vacancy (VC) with a demonstrated detrimental effect on the minority carrier lifetime in 4H-SiC epitaxial layers. Hence, a variety of methods for VC removal have been proposed. Common to all is that they involve some sort of C-injection into the epi-layer that leads to annihilation of VC with C interstitials (Ci) via the reaction Ci＋ VC→0̸. However, many studies on injection of Ci for removal of VC do not take into account the potential effect of any additional defects that are formed as a result of excess C in the material, including electrically active defects that introduce energy levels in the SiC band gap. Herein, we study the formation and impact of carbon related defects that are introduced in 4H-SiC epi-layers by injection of excess carbon. C-injection is achieved by annealing 4H-SiC epi-layers covered by a graphitized photoresist known as a C-cap at 1250°C for different durations. The resulting appearance of defects in the samples is monitored using deep level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS) measurements, which reveal the formation of both minority and majority carrier traps as a result of the C-injection. Intriguingly, the injected carbon is also found to interact with a perennially present impurity in 4H-SiC epi-layers and a potentially lifetime limiting defect, namely boron. Furthermore, we monitor the minority carrier lifetime as a function of C-injection time and depth from the surface using cross-sectional time-resolved photoluminescence (TRPL) measurements. Both the defect distributions and the minority carrier lifetime are found to depend strongly on the duration of the C-cap anneal, with a marked depth dependence being present for all samples studied. The moderate temperature C-cap annealing treatment is proposed as a method for enhancing the carrier lifetime in n-type 4H-SiC epi-layers for power device applications.

Development of n-type epitaxial growth on 200 mm 4H-SiC wafers for the next generation of power devices

Driven by the spread of electric vehicles, the market for SiC power devices is expanding so rapidly that many suppliers are struggling to meet the customer's demand both in terms of final devices and raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 in.). STMicroelectronics (ST), world leader in the sale of SiC power device, has reacted by starting the in-house production of the next-generation wafers with a diameter of 200 mm (8 in.). This work describes the optimization of the n-type 4H-SiC epilayers on 200 mm substrates performed by ST in collaboration with LPE® “an ASM company” (LPE). The density of defects and the thickness and doping uniformity of the epilayers grown on 200 mm substrates are characterized, showing results comparable to the ones obtained for standard 150 mm wafers. Also, the reproducibility of the manufacturing process is improved, resulting in a run-to-run variation of the epilayer's thickness and doping below 2%.

Enhanced Hole Transport in Ni/Y₂O₃/n-4H-SiC MOS for Self-Biased Radiation Detection

We report the fabrication of novel self-biased high resolution radiation detectors achieved in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices. Vertical MOS structure has been realized by pulsed laser deposition of 40 nm Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer on 20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> n-type 4H-SiC epilayer followed by sputter coating a nickel gate, which revealed a record-high hole diffusion length. The MOS device exhibited a remarkable radiation detection response to 5486 keV alpha particles with a charge collection efficiency of 82% and an energy resolution of 72 keV full width at half maximum (FWHM) at zero applied bias. The hole diffusion length has been calculated to be 56 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> using a drift-diffusion model. Such long hole diffusion length and a flat-band potential of 2.1 V, enabled to attain high efficiency and resolution in the self-biased mode. Band energy calculations indicated that the presence of Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer may have neutralized the hole traps usually present in a metal-4H-SiC interface thereby substantially improving the hole transport. Such high performing self-biased radiation detectors fabricated on 4H-SiC are intended for applications in harsh environment space missions, wherein carrying detector power supplies as a payload becomes a critical logistic issue. The present study opens the high potential of other wide bandgap semiconductors as self-biased MOS devices as well.

Limited current conduction due to various types of stacking faults in n-type 4H-SiC epilayers

Impacts of various types of stacking faults (SFs) on electron conduction in an n-type 4H-SiC epilayer were experimentally investigated. N-type Schottky barrier diodes were fabricated, containing a SF plane in the active area with a covering ratio of unity, whereupon the current–voltage characteristics were evaluated within a temperature range of 293–523 K. The forward current was significantly limited due to the SFs, the degree of which depended on the type of SF, and the current limitation was moderated by increasing the temperature. These results could be consistently explained by the well-known quantum well model.

Analysis of carrier lifetimes in N + B-doped n-type 4H-SiC epilayers

Control of carrier lifetimes in nitrogen (N)-doped n-type 4H-SiC epilayers was attempted by intentional boron (B) doping. Doping concentrations of B were controlled to be within 1015–1018 cm−3 by varying the triethyl boron flow rate during epitaxial growth. Time-resolved photoluminescence measurements for the band edge luminescence of the N + B-doped epilayer showed a fast decay time of less than 30 ns under a low injection level at 300 K, while a slow decay component was observed at elevated temperatures of 423–523 K. To understand the mechanism of carrier capture and recombination in N + B-doped 4H-SiC, excess carrier decay curves were simulated by solving rate equations with a simple model. As an effective “recombination enhancing layer,” the 1.6-μm-thick N + B-doped (N: 4 × 1018 cm−3, B: 7 × 1017 cm−3) buffer layer in the PiN diode showed increased intensity of D center-related electroluminescence with increasing injected hole concentrations and prevented the formation of stacking faults from basal plane dislocations in the substrate even at the injection level of 1 × 1016 cm−3 at the interface between the drift and buffer layers.

Wide-ranging control of carrier lifetimes in n-type 4H-SiC epilayer by intentional vanadium doping

Wide-ranging control of carrier lifetimes in n-type epilayers by vanadium (V) doping is attempted toward not only developing a buffer layer to prevent the stacking fault expansion but also improving switching loss in 4H-SiC-based bipolar devices. Control of V doping concentrations in lightly and highly nitrogen (N)-doped epilayers was achieved within the range of 1012–1015 cm−3 by changing the input flow rates of vanadium tetrachloride. Photoluminescence (PL) and deep-level transient spectroscopy analyses revealed that incorporated V atoms create the PL bands within the range of 0.8–1.0 eV, and densities of the deep center at the V3+/4+ acceptor level (Ec − 0.97 eV) increase linearly with V doping concentrations. Accordingly, V doping shortens the minority carrier lifetimes in lightly N-doped epilayers from 3 μs to 40 ns as well as lifetimes in highly N-doped epilayers down to 20 ns at 20 °C, achieving intrawafer carrier lifetime uniformities of 3–10% σ/mean. Furthermore, V doping during epitaxial growth exhibited a nonsignificant memory effect and the V-doped epilayers showed high thermal stability against postprocessing by 1700 °C. We also demonstrated PiN diodes with a 2.4 μm-thick N + V-doped buffer layer (N: 1 × 1018 and V: 1 × 1014 cm−3), showing no degradation after a stress test for 1 h under a direct current density of 600 A/cm2.

Electrically active deep levels formed by thermal oxidation of n-type 4H-SiC

The doubly negative charge state of the carbon vacancy is a lifetime killer defect in n-type 4H-SiC. One way to reduce the concentration of this defect is by thermal oxidation. In this study, we electrically characterized n-type 4H-SiC epilayers that underwent dry thermal oxidation. While we confirm that the reduction of VC is accompanied by the formation of the previously identified ON1 and ON2 levels, we additionally report on the presence of two new shallow levels. These are found at 0.19 and 0.24 eV below the conduction band edge. Their nature is discussed on the basis of their thermal stability and formation kinetics. The former was studied up to 1600 °C, whereas the latter was carried out by performing oxidation in the 1200–1300 °C temperature range and in the 45 min-24 h time range.

Recombination and diffusion processes in electronic grade 4H silicon carbide

Carrier dynamics in n-type 4H-SiC epilayers of varying thicknesses and low Z1/2 defect concentrations are investigated here in wide ranges of excess carrier density and temperature. Several techniques are employed to monitor carrier diffusion and recombination processes, including light induced transient grating (LITG), microwave photoconductance decay (MPCD) and free carrier absorption (FCA) using ps-laser pulses at 355 nm. The observed increase of the diffusion coefficient with the increasing excitation level is explained by the transition from the minority to the bipolar transport regime. Its subsequent decrease with even higher excitations is found to be governed by band-gap renormalization and degeneracy effects. The bulk lifetime, limited by hole traps at 0.19–0.24 eV above the valence band at lower excitations, was found to decrease from few microseconds to hundreds of nanoseconds during the transition regime from the minority to the bipolar transport. Our temperature-dependent measurements confirmed the trap activation energy and provided the approximate functional form of electron and hole lifetimes as τe = 340 × (T/300 K)3/2 ns and τh = 100 × (T/300 K)–1/2 ns, for the temperature T range 80–800 K. It was found to hold for 65 and 120 μm sample thicknesses, while the lifetimes were found to be twice shorter for the sample 35 μm thick.

Time-resolved photoluminescence spectral analysis of phonon-assisted DAP and e-A recombination in N+B-doped n-type 4H-SiC epilayers

It is crucial to clarify the roles of phonon-assisted donor-acceptor pairs (DAPs) and free-to-acceptor (e-A) emissions in n-type 4H-SiC doped with nitrogen (N) and boron (B), where N and B induce the shallow donor and the D center (deep B) acceptor levels, respectively, in order to understand the complicated carrier recombination mechanism, as well as developing fluorescent SiC with a high color rendering index by controlling the ratio of the two overlapped emissions. Here, time-resolved photoluminescence (TRPL) spectral analyses were performed, in which phonon-assisted DAPs and e-A components were individually recognized. The D center-related green luminescence (1.6–2.8 eV) shows a non-exponential decay followed by a very slow decay in TRPL measurements at room temperature (RT). It emerges that most of the DAP emission intensities decay much faster than e-A emissions and contribute to what is initially fast and non-exponential decay at low temperatures, while the slow decay at RT is mainly from e-A emissions. At a much higher temperature, such as 473 K, only the e-A emission remains and the decay transforms from non-exponential to exponential behavior. High-temperature thermal quenching of e-A emissions exhibits different behaviors for samples with differing B doping concentrations. An activation energy of 0.6 eV was estimated from the Arrhenius plot of e-A emission intensity from a B-doped sample, which matches the D center level. This indicates that the hole thermal emission rate is greatly enhanced at a high temperature, which accelerates the decay of e-A emission intensity at high temperatures.

Growth and characterization of nitrogen-phosphorus hybrid passivated gate oxide film on N-type 4H-SiC epilayer

A novel nitrogen-phosphorus (N&P) hybrid passivation technique by NO-containing dry oxidation of phosphorus-implanted 4H-SiC epilayer has been proposed to grow high-property gate oxide film. For demonstration and contrast, n-type 4H-SiC MOS capacitors with N&P hybrid and only N passivation have been fabricated and tested. The results from Secondary Ion Mass Spectroscopy (SIMS) reveal that about 60% of the implanted phosphorus atoms remain in the SiO2 film after sacrificial oxidation of the implantation layer. And the distribution of phosphorus is approximately uniform throughout the grown SiO2 film with a concentration about 4 × 1019 cm−3, avoiding the SiO2 film converting to phosphosilicate glass (PSG). I-V and X-ray Photoelectron Spectroscopy (XPS) data show that the grown SiO2 film with the appropriate phosphorus passivation can effectively improve the quality of oxide film, leading the gate oxide bandgap and integrity improved and reducing the leakage current above two orders of magnitude. The bias stress measurements with ultraviolet light (UVL) irradiation also show that the N&P hybrid passivation treatment can completely restrain the near-interface electron traps (NIETs) in 4H-SiC MOS devices, indicating that incorporation an appropriate amount of phosphorus atoms in the grown SiO2 film also can make the electron trap density reduced effectively.

(Invited) Thermal Stability of 1×1020 cm-3 Al+ Implanted 4H-SiC after Electrical Activation at Temperature ≥ 1850°C

In 4H-SiC electronic devices, Al+ ion implantation is often used to obtain selected regions of desired p-type conductivity in n-type epitaxial layers. A mandatory high temperature annealing is necessary after the implantation process for the electrical activation of the implanted Al. The temperature of the former and the density of the latter vary in the range 1600-1950°C and 1017-1020 cm-3, respectively. The switching properties of the so obtained bipolar junctions depend on carrier life-time in the n-type 4H-SiC epitaxial layers after processing. In the literature, it has been shown that carbon vacancy VC in n-type 4H-SiC epi-layers is a carrier life-time killer defect and that its concentration, after high temperature treatments in the range 1500-1950°C, saturates on values that are higher the higher are the applied temperature and cooling rate [1]. It has been also shown that, in the case the thermally treated 4H-SiC epi-layers were ion implanted, and whatever is the implanted ion species, VC annihilation took place from 1000°C till 1500°C, while at 1600°C the phenomena of VC annihilation and VC formation seem to compete [2], suggesting that up to 1500°C, a carbon interstitial IC’s injection from the implanted near-surface layer into the epi-layer can be sufficient to make dominant VCannihilation, but this is not the case at 1600°C. Our previous studies on carrier life-time in Al+ implanted p+-n-n+ diodes, with 6×1019 cm-3 and 2×1020 cm-3 Al+ implanted emitters after 1600 °C/20 min without carbon-cap (C-cap) and 1950 °C/5 min with C-cap post implantation annealing, respectively, have shown longer carrier life-time for diodes annealed at the lower temperature, about 700 ns against 170 ns [3], as measured by open circuit voltage decay (OCVD). The diodes annealed at the higher temperature have shown, by DLTS spectroscopy, a VC concentration lower by a factor ~ 3 relative to that in as-grown epi-layers subjected to almost the same thermal annealing (1950 °C /3 min) [1]. If the ion dose is sufficiently high, it is reasonable that injection of IC’s from the implanted layer into the epi-layer bulk takes place even at temperatures as high as 1950 °C but thermal generation of VCstill remains the prevailing process. Taking into account the above results, it sounds reasonable to deserve efforts to the investigation of an ion implantation technology for bipolar junction in 4H-SiC where the electrical activation of the implanted species is achieved by a high temperature treatment and the degradation of the carrier life-time in the device drift layer is rescued by a subsequent low temperature treatment. The first step towards such a technology is to verify that during the thermal treatment for carrier life-time rescue, none or negligible deactivation of the electrically activated dopant takes place. This is the purpose of this study. 4H-SiC materials, both high-purity-semi-insulating (HPSI) and low doped n-type, have been implanted with Al+ ions so to obtain a homogenous doped layer next of the wafer surface. Post implantation annealing has been performed at 1950°C for different times in the range 5-40 min. Some samples have been also thermally treated at 1500°C for 40 min or for 240 min. During every annealing, the sample were protected by a pyrolyzed resist film (C-cap), that was removed after the last thermal treatment. The implanted Al concentration was 1×1020 cm-3, that is lower than Al solubility in 4H-SiC at 1950°C, and higher than the expected, but never measured, Al solubility in 4H-SiC at 1500°C [4]. Van der Pauw devices were used for Hall effect and sheet resistance measurements in the temperature range 180-680 K. The temperature dependences of these data show that the 1500°C treatment has an effect ranging from “neutral” to “beneficial” on the electrical transport of the Al+implanted 4H-SiC layer submitted to a 1950°C annealing immediately after implantation. This result opens the way towards the fabrication of bipolar diodes with p-type emitters of almost identical hole density but different thermal treatments after implantation, thus with drift layers that might have very different current transport properties. [1] H. M. Ayedh, V. Bobal, R. Nipoti, A. Hallén, B. G. Svensson, J. Appl. Phys. 115, 012005 (2014) [2] H. M. Ayedh, A. Hallén, B. G. Svensson, J. Appl. Phys. 118, 175701 (2015). [3] H. M. Ayedh, M. Puzzanghera, B. G. Svensson, R. Nipoti, Mater. Sci. Forum 897, 279-282 (2017) [4] M. K. Linnarson, U. Zimmermann, J. Wong-Leung, A. Shoener, M.S. Janson, C. Jagadish, B. G. Svensson, Appl. Surf. Sci. 203-204, 427-432 (2003).

(Invited) 4H-SiC Ion Implanted Bipolar Junctions: Relevance of the 1950°C Temperature for Post Implantation Annealing

Ion implantation is a relevant technology for the fabrication of p-n interfaces in several SiC electronic devices; ion implanted source/drain and body regions in commercial 4H-SiC MOSFET [1] and buried grids in JBSD [2] can be cited as examples. Previous studies have shown that the efficiency of the electrical doping by ion implantation increases with the increase of the post implantation annealing temperature [3-4] and time [5]. Previous studies have also shown that n-type 4H-SiC epi-layers treated at so high temperatures as those used for the post implantation annealing of 4H-SiC, contain Z1/Z2 defect concentrations of increasing values with the increase of the processing temperature [6-7]. Z1/Z2 is a lifetime killer defect is 4H-SiC [8]; it is always present at the same time that the EH7 defect. Z1/Z2 and EH7 are univocally associated to the double acceptor state at 0.7 eV from the conduction band (CB) and the single donor one at 1.55 eV from CB, respectively, of the structural defect carbon vacancy Vc in 4H-SiC [9]. This presentation will highlight two recent results obtained by the use of the 1950°C temperature for the post implantation annealing of Al+ ion implanted 4H-SiC. One result concerns the hole transport in very heavy doped 4H-SiC(Al) layers. The other result concerns the defects that may account for the area component of the forward characteristic of vertical 4H-SiC p-i-n diodes with Al+implanted anodes. The very efficient electrical activation process at 1950°C and an Al implanted concentration above the Al solubility limit of 2x1020 cm-3 in 4H-SiC [10] allow us to obtain p-type 4H-SiC(Al) materials with a conductivity temperature dependence that is consistent with an hole transport through impurity band states and in particular through a variable range hopping mechanism at temperatures that ranges from below till around room temperature, depending on the value of the implanted Al concentration. Positive and negative drawback for application of these doping conditions in practical SiC devices will be discussed. 4H-SiC p-i-n vertical diodes with Al+ implanted anodes and different perimeter to area ratios have been used to obtain the area and perimeter component of the forward and reverse current-voltage (I-V) curves of a batch of diodes obtained with a post implantation annealing temperature of 1950°C [11]. It is worthwhile to remark that the specific area and perimeter curves are typical of processing and of 4H-SiC material parameters, i.e. they are independent of the device geometry [12-13]. Thermal activation energies of 1.65 eV, 0.5 eV and 0.2 eV have been obtained for the defects responsible of generation and recombination currents of this diodes batch. These energy values may be the labels of different types of defects in 4H-SiC, both impurities and intrinsic defect (Vc in particular). These hypotheses have been used in the Synopsys Sentaurus TCAD suite [14] for fitting the forward area current density of the studied diodes. Fig. 1 shows an example of the simulation outputs in the case of traps associated to the three level obtained from the diode I-V curves. Electron and hole carrier life-times are the fitting parameters of this study. Other point defects will be considered and the life-time values for reproducing experimental data will be discussed with respect to the processing parameters used during diode fabrication. [1] last accessed on April 7, 2016: http://www.wolfspeed.com/power/products/sic-mosfets [2] J.-K. Lim, D. Peftitsis, D.-P. Sadik, et al., Mater. Sci. Forum 778-780 (2014) 804-807. [3] R. Nipoti, R. Scaburri, A. Hallén, et al., J. Mater. Res. 28 (2013) 1-6. [4] R. Nipoti, A. Nath, S.B. Quadri, et al., J. Electron. Mater. 41 (2012) 457-465. [5] R. Nipoti, A. Parisini, S. Vantaggio, et al. Mater. Sci. Forum 858 (2016) 523-526. [6] H. M. Ayedh, V. Bobal, R. Nipoti, et al., J. Appl. Phys. 115, 012005 (2014). [7] H. M. Ayedh, A. Hallén, and B. G. Svensson, J. Appl. Phys. 118, 175701 (2015). [8] P. B. Klein, B. V. Shanabrook, S. W. Huh, A. Y. Polyakov, et al., Appl. Phys. Lett. 88, 052110 (2006). [9] N. T. Son, X. T. Trinh, L. S. Løvlie, B. G. Svensson, et al., Pys. Rev. Lett. 109, 187603 (2012). [10] M. K. Linnarsson, U. Zimmermann, et al., Appl. Surf. Science 203-204 427 (2003). [11] M. Puzzanghera and R. Nipoti, Mater. Sci. Forum 858 (2016) 773-777. [12] U. Grossner, F. Moscatelli, and R. Nipoti, Mater. Sci. Forum 778-780 (2014) 657-660. [13] A. Nath, Mulpuri V. Rao, et al., IEEE proceedings "Ion Implantation Technology (IIT), 2014 20th International Conference on", Portland, OR, USA, pp. 1-4. [14] last accessed on March 23, 2016: http://www.synopsys.com/Tools/TCAD Figure 1

Control of carrier lifetime of thick n-type 4H-SiC epilayers by high-temperature Ar annealing

We investigated the carrier lifetime and Z1/2 center density of thick n-type 4H-SiC epilayers, which were oxidized and subsequently annealed in Ar at high temperatures. The Z1/2 center density decreased below the detection limit in the region to, at least, a 130 µm depth by thermal oxidation. After subsequent high-temperature annealing, the Z1/2 center density increased with increasing annealing temperature, while the distribution of the Z1/2 center density was nearly uniform to a 130 µm depth. The carrier lifetime could be controlled from 26 to 2.4 µs by changing the annealing temperature from 1600 to 1800 °C.

Improved n-Type 4H-SiC Epitaxial Radiation Detectors by Edge Termination

A new edge termination with ${\rm SiO}_{2}$ and ${\rm Si}_{3}{{\rm N}_4}$ passivating layers has been developed and is shown to be a very effective method for improving energy resolution of $20 ~\mu \hbox{m}$ n-type 4H-SiC epilayer Schottky barrier radiation detectors. The junction properties of the fabricated detectors before and after edge termination were studied by current-voltage (I-V) and capacitance-voltage (C-V) measurements. A thermionic emission model applied to the forward I-V characteristics showed surface barrier height of $\sim 1.4 ~\hbox{eV}$ and diode ideality factor of $\sim 1.1$ . The C-V measurements showed a doping concentration of $1.8 \times {10^{14}} ~\hbox{cm}^{ - 3}$ which ensured a fully depleted ${(\sim 20 ~\mu \hbox{m})}$ detector at bias voltages as low as $\sim 70 ~\hbox{V}$ . Alpha spectroscopy measurements revealed an improved energy resolution from $\sim 0.7 \% $ to $\sim 0.4\% $ for 5.48 MeV alpha particles. Deep level transient spectroscopy (DLTS) measurements have shown a decreased concentration of ${{\rm Z}_{1/2}}$ defect levels in detectors following edge termination.

Development of a microwave photoconductance measurement technique for the study of carrier dynamics in highly-excited 4H-SiC

The microwave conductance decay (MCD) technique combining an initially matched transmission line setup and picosecond optical excitation was developed and applied for the monitoring of transmitted and reflected microwave power transients in a 4H-SiC epilayer in a wide excitation range, from 2 × 1014 to 1018 cm−3. The excitation-dependent decrease in measurement sensitivity in the power-law relations of the transients was observed at excess carrier densities above 1016 cm−3 due to the line mismatches and decrease in the internal microwave field in the illuminated sample. The calibration procedure of MCD data on excess carrier density was applied for the correction of the MCD transients and resulted in nearly identical MCD kinetics in the reflection and transmission. In a 35 μm-thick n-type 4H-SiC epilayer, the tendencies of the gradual decrease of the initial decay time with an excitation increase and the excitation-enhanced carrier recombination rate in MCD tails were analyzed numerically. These tendencies were attributed to the excitation dependent surface recombination rate and the enhanced trap-related bulk recombination, correspondingly.

MOS Interface Characteristics of &lt;i&gt;In Situ&lt;/i&gt; Ge-Doped 4H-SiC Homoepitaxial Layers

We report on the electrical characterization of the Metal-Oxide-Semiconductor (MOS) interfacerealized on in-situ Ge-doped n-type 4H-SiC epilayers grown by Chemical Vapour Deposition(CVD). In order to study the relevance of this novel material for MOSFET technology, and in particularwhether the Ge presence deteriorates the SiC/SiO2 interface, we investigated the electrical propertiesof MOS capacitors realized on this novel substrate. Capacitance-Voltage measurements, performedto determine the quality of the SiC/SiO2 interface, show that the interface traps concentration is notincreased by the Ge content. The current through the oxide layer, monitored to study the bulk oxidequality and the tunneling mechanisms, indicates that Fowler-Nordheim conduction occurs and that thesubstrate-to-oxide barrier for electrons is comparable to the reported values for the SiC/SiO2 system.

Comparative Study of n-Type 4H-SiC: Raman vs Photoluminescence Spectroscopy

This paper presents a comparative optical and vibrational spectroscopy study of diversely n-type 4H-SiC epilayers. It is shown that in order to determine the nitrogen doping in a wide range (1016 up to few 1019cm-3) the two techniques are complementary. Moreover only the LTPL provides the information about the compensation and nature of the dopant species.

Effect of Phosphorus Implantation Prior to Oxidation on Electrical Properties of Thermally Grown SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC MOS Structures

The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions.

Decay curve analyses in carrier lifetime measurements of p- and n-type 4H-SiC epilayers

The impacts of the ambipolar diffusion constant and surface recombination in carrier lifetime measurements of p- and n-type 4H-SiC epilayers are investigated in detail by comparing a numerical simulation based on a diffusion equation and the measurement of microwave photoconductance decay (µ-PCD) curves measured from 4H-SiC epilayers. The simulation reveals that the shapes of decay curves of excess carrier concentration in epilayers, which defines the effective carrier lifetime, are different between p- and n-type 4H-SiC under a low-level injection condition, even when the bulk lifetime and the surface recombination velocity are fixed to the same values for p- and n-type epilayers. In experiments, the shapes of the microwave photoconductance decay curves measured from p- and n-type 4H-SiC epilayers show a similar tendency to the simulation results under a low-level injection condition. This is attributed to the difference in the dependence of the ambipolar diffusion constant on the excess carrier concentration for p- and n-type 4H-SiC. The comparison of µ-PCD decay curves obtained from 50-µm-thick epilayers with different surface passivation indicates that the surface recombination velocity on the epilayer passivated with deposited SiO2 followed by NO annealing is about one order of magnitude lower than that of the epilayer passivated with the dry oxide.

Multi-Cycle High Temperature Rapid Thermal Annealing for Dislocation Elimination in 4H-SiC Epitaxy

High power devices fabricated in 4H-silicon carbide (SiC) epilayers are known to suffer from forward voltage degradation caused by basal plane dislocation (BPD) induced stacking faults (SF) [[1], [2]]. Over the past decade, several efforts have been successful in removal of more than 90% of the BPDs in the substrate by converting them to benign threading edge dislocations (TED) during epigrowth [[3], [4]]. However, BPDs in the many areas of the epilayers are still > 100 cm-2, which adversely affects the device yield and reliability. We have developed a technique to remove the existing BPDs from the epilayers by using a novel multi-cycle rapid thermal annealing (MRTA) process [[5]], where the BPDs in the epilayers were eliminated, while preserving the epitaxial surface.We used 4 offcut, 15 mm, n-type 6E15 4H-SiC epilayers, commercially obtained. The as-grown samples were imaged using ultraviolet photoluminescence (UVPL) imaging. Carriers were excited with the 334 nm line from an Ar-ion laser, and images were collected in the emission range of 600-1000 nm. The samples were graphite capped and annealed at 1750 oC-1875 oC for a total time of ~5 minutes in 20 cycles. The annealing was performed in a custom designed chamber with inductive sample heating and ultrapure N2 overpressure at 0.41MPa. The base temperature was maintained near 1500 oC, from where the temperature was ramped up and down to the desired temperature in rapid cycles to get an accumulated time of 5 mins at the desired temperature. The combination of high N2 overpressure and rapid cycles enabled us to perform the anneals at a higher temperature than conventional methods, while preserving the graphite cap, and thus maintaining a pristine epitaxial surface. Post-annealed samples were also imaged to observe the BPDs in the epilayers. The UVPL images of the as grown samples showed an average BPD density ~1000 /cm2. We wanted to achieve two goals with our annealing efforts, which were to eliminate BPDs in the epitaxial layers and to preserve the epitaxial surface morphology. We conducted several previous attempts to anneal similar samples using high temperature microwave annealing as well as annealing under high N2 pressure. From our work with microwave annealing, we were able to eliminate BPDs by annealing at above 1750 oC. However, the surface morphology was poor. The graphite capping technique was tweaked but the microwave annealing performed at ambient pressure conditions was not able to achieve a good sample surface. Annealing under high pressure preserved the surface, however, could not go to temperatures higher than 1750 oC without damaging the cap. For complete BPD elimination much higher temperature annealing was required. Thus, the novel MRTA process was adopted, which went to higher temperatures and preserved the graphite cap. Results from the post annealed samples using the different techniques would also be presented.The UVPL images of the samples after the MRTA process indicated a surface without any significant pits or generation of any new BPDs during the annealing process, which has been shown to happen using conventional annealing at these high temperatures. Almost all the BPDs that were previously present disappeared in the epilayer. It is proposed that during annealing BPDs that had not yet converted to threading edge dislocations (TED) during epigrowth forms a TED near the surface. Then the TEDs at the end of all the BPDs glide in a prismatic plane causing the BPD to shorten. Since this glide doesn't occur in the lower energy basal plane, the required energy for this glide is provided by the very high annealing temperature. This way a BPD segment converts to a TED with the TED glide and thus shortens the BPD. The UVPL images of the annealed samples also show a dot where the original BPD had propagated from the substrate, which represents a TED.[[1]] J. P. Bergman, Mater. Sci. Forum 353, 299 (2001)[[2]] R. E. Stahlbush, Mater. Sci. Forum 389, 427 (2002)[[3]] S. Ha, Phys. Rev. Lett. 92, 175504 (2004)[[4]] R. L. Myers-Ward, Mat. Sci. Forum 615-617, 105 (2009)[[5]] T. J. Anderson, Elect. Lett. 50, 197 (2014)Figure: Typical UVPL image of as grown sample with BPD density ~1000 /cm2. The short horizontal white lines are BPDs. Lower image is sample after MRTA at 1875 oC for 5mins, with no BPDs. The long scratch line is scribe mark on backside.