N-path Filter Research Articles

Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

This paper presents a wide-frequencyrange, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal S22 and S11 matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in 0.13 μm, 1-poly, 6-metal CMOS technology. The die area of the transceiver is 4 mm x 3 mm. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

Broadband Synthetic Transmission-Line N-Path Filter Design

A synthetic transmission-line N-path bandpass filter technique that lowers the in-band insertion loss and increases the out-of-band rejection of the traditional N-path filter is analyzed. The performance limitations of the traditional N-path filter in terms of in-band insertion loss and limited rejection are reviewed. Measurement results from 0.1 to 1.6 GHz of a single-ended, four-stage synthetic transmission-line N-path filter fabricated in a 65-nm CMOS technology that achieves less than 5-dB insertion loss across the tuning range, 30–50-dB out-of-band rejection, in-band third-order distortion input-referred intercept point (IIP3) of $+$ 29 dBm, and a $+$ 11-dBm input-referred 1-dB compression point $({\rm P}1{\rm dB}_{\rm Jam})$ out-of-band jammer tolerance are presented.

A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS

This paper presents a high-performance two-path wideband receiver (RX) for 4G LTE applications. The RX uses an extra GM stage after the LNA to improve the noise figure (NF). Furthermore, different RF and baseband blocker rejection techniques are proposed to significantly improve the linearity of the RX. The blockers are first rejected after the LNA stage through an N-path filter. Then, a novel base-band blocker filtering (BBBF) technique improves IIP3 by 7 dB. A dual-mixer architecture is also employed to attenuate blockers both before and after the mixer stage. The N-path filter noise is sensed out-of-phase by the RX main path and cancelled at the inputs of the shared TIA. The RX achieves 1.8 dB NF with 50 dB gain at 2 GHz in 40 nm CMOS technology. The RX out-of-band IIP3 is +5 dBm, which is improved by 20 dB employing the proposed techniques, while consuming 36 mW.

A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters

This paper presents the analysis and design of a quadrature charge-domain down-conversion sampling mixer with embedded finite-impulse-response (FIR), infinite-impulse-response (IIR), and 4-path bandpass filters. An in-depth investigation of the principles of periodic impulse sampling, periodic windowed sampling, and periodic N-path windowed sampling is presented and their characteristics are compared. A detailed mathematical treatment of charge-domain windowed samplers with built-in sinc, FIR and IIR filters is provided. A quadrature charge-domain sampler with embedded FIR, IIR, and 4-path band-pass filters is proposed and its performance including the effect of the non-idealities of devices is investigated. The proposed design is implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results demonstrate that the proposed design is tunable over 50–250 MHz frequency range. For an 100 MHz input, the proposed design exhibits 70 dB aliasing rejection, 60 dB stop band attenuation while consuming current of 145 $\mu{\rm A}$ . The performance of the proposed design is further validated using the results of on-wafer measurement of the fabricated microchip.

Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance

N-path filters exploiting switched-series-R-C networks can realize high-Q blocking-tolerant band-pass filters. Moreover, their center frequency is flexibly programmable by a digital clock. Unfortunately, the time variant nature of these circuits also results in unwanted signal folding. This paper proves analytically that folding can be reduced and band pass filtering can be improved by adding an inductance in series with the switched-R-C network. In contrast, a shunt capacitor degrades band-pass filter performance. The interaction between the reactive series impedance and the switched capacitors of an N-path filter complicates analysis due to memory effects associated with reactive components. Assuming N identical signal paths with 1/ N duty cycle, we show it is possible to solve the set of differential equations, by assuming that the signals in each path only differ in delay. Analytical equations are verified versus simulations, and the benefits in filter properties and reduction in signal folding are demonstrated.

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high- $Q$ filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7–2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of $+$ 1 dBm.

Wideband Receivers: Design Challenges, Tradeoffs and State-of-the-Art

A universal wideband receiver supporting multi-band multi-standard wireless communications offers the prospective for cost reduction and flexibility improvement of next-generation handheld devices. Unlike the traditional narrowband receivers that are tailored for specific standards and are assisted by dedicated SAW filters to restrict the input signals (frequency and power), SAW-less wideband receivers are fully exposed to the dynamic spectrum conditions, stimulating circuits and systems innovation to surmount the challenges while keeping up the integration level, power and area efficiencies. This article outlines the design challenges and fundamental tradeoffs of wideband receivers, and describes how they can be addressed by three circuit techniques: noise cancelling, N-path filtering and N-path mixing improving the noise figure, out-of-band linearity and harmonic-rejection capability, respectively. Case studies of silicon-proven solutions representing the state-of-the-art are included, illustrating the pros and cons of different implementation and combination of such three techniques. Architecturally those wideband receivers can be classified as: i) current-mode passive-mixer receiver; ii) voltage-mode passive-mixer receiver; iii) current-mode active-mixer receiver, and iv) current-mode parallel active/passive-mixer receiver. This article should be relevant to junior designers preparing to jump-start in this evolving field, and experience designers intended to collectively compare the existing solutions before further development.

A 2.5-GHz Receiver Front-End With <formula formulatype="inline"> <tex Notation="TeX">$Q$</tex></formula>-Boosted Post-LNA <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula>-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

A CMOS Broadband Distributed <formula formulatype="inline"><tex Notation="TeX">${\rm N}$</tex></formula>-Path Tunable Bandpass Filter

A distributed CMOS N-path tunable band-pass filter (BPF) technique is introduced to lower the in-band insertion loss and increase the out-of-band rejection of the traditional N-path filter. Measurements from 0.3 to 1.6 GHz demonstrate a tunable BPF with 31 to 53 dB out-of-band rejection in a 65 nm process.

Design of Active N-Path Filters

A design methodology for synthesis of active N-path bandpass filters is introduced. Based on this methodology, a 0.1-to-1.2 GHz tunable 6th-order N-path channel-select filter in 65 nm LP CMOS is introduced. It is based on coupling N-path filters with gyrators, achieving a “flat” passband shape and high out-of-band linearity. A Miller compensation method is utilized to considerably improve the passband shape of the filter. The filter has 2.8 dB NF, +25 dB gain, +26 dBm wideband IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ( MHz), an out-of-band 1 dB blocker compression point B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB,CP</sub> of +7 dBm (Δf = +50 MHz) and 59 dB stopband rejection. The analog and digital part of the filter draw 11.7 mA and 3-36 mA from 1.2 V, respectively. The LO leakage to the input port of the filter is ≤-64 dBm at a clock frequency of 1 GHz. The proposed filter only consists of inverters, switches and capacitors and therefore it is friendly with process scaling.

An N-Path Enhanced-Q Tunable Filter With Reduced Harmonic Fold Back Effects

A high-Q, tunable, bandpass filtered amplifier structure is proposed which is based on a novel Q enhancement technique in N-path filters. Using Fourier series analysis, frequency response of an N-path filter as well as the aliasing effects which are present in it are derived. Frequency translation of unwanted contents at higher frequencies to the center frequency of the bandpass filter is called harmonic fold back (HFB). It is shown that using an additional N-path filter with the same clock frequency but different clock phases can reduce the HFB. The required conditions for fold back elimination are derived from Fourier series expansion analysis. In order to achieve HFB reduction as well as increasing stop-band rejection and Q factor, an LNA containing an N-path filter is added to each of the two filters. The LNA in the proposed structure is designed for high linearity and low NF, utilizing noise and distortion cancellation methods. The filter is designed and simulated in 0.18 um CMOS with an ideal balun. The voltage gain is 17.5 dB across the 0.25-1 GHz frequency band, while achieving a NF between 2.2 to 2.4 dB, an IIP3 between -2 to +2 dBm, HFB attenuation of between 25 to 45 dB and power consumption of 4.5 mW for each LNA. Finally, the proposed filter (with 4-path sub-filters) is simulated and compared to filters with 4-path and 8-path sub-filters without the proposed built-in HFB reduction.

Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50-Ω environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4-2.8 dB. The rejection at the notch frequency is 21-24 dB, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> > +2 dBm, and IIP3 > +17 dBm.

Widely Tunable 4th Order Switched G$_m$-C Band-Pass Filter Based on N-Path Filters

A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> -C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of the two 4-path BPFs and increase their quality factors. The filter is tunable from 0.4 GHz to 1.2 GHz with approximately constant bandwidth of 21 MHz. The in-band 1-dB compression point of the filter is -4.4 dBm while the in-band IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of the filter is +9 dBm and the out-of-band IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is + 29 dBm (Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> =+50 MHz). The ultimate rejection of the filter is >; 55 dB and the NF of the filter is 10 dB. The static and dynamic current consumption of the filter are 2.8 mA from 2.5 V and 12 mA from 1.2 V, respectively (at 1 GHz). The LO leakage power to the input port is <; - 60 dBm. The filter has been fabricated in CMOS LP 65 nm technology and the active area is 0.127 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification

A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-$</tex></formula> 3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm P}_{\rm 1dB}=2\ $</tex></formula> dBm and the noise figure is 3–5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).

Necessary and sufficient conditions for time-invariant operations of N-path filters

Necessary and sufficient conditions on the modulating functions for a digital N-path filter (NPF) to be shift-invariant are obtained. Previously used conditions are sufficient but not necessary. These new conditions allow NPFs to be designed with the smallest number of paths without the need of pre- and postfiltering by ideal low-pass filters. Some design examples are presented. >

Accurate simulation of nonlinear switched capacitors and sampled circuits by harmonic balance and related techniques

The Letter shows the ability of harmonic balance and related techniques to handle high speed sampled circuits, enabling a complete nonlinear simulation of such circuits. As an example, the simulation of an N-path filter using the harmonic balance method is achieved. A comparison between simulations and measurements of the transfer characteristic is shown and the accuracy and convenience of the proposed method are demonstrated. This technique will allow unification of the simulation tools of nonlinear mixed analogue/digital monolithic circuits to derive the transfer function, conversion noise and saturation characteristics.

Realizations of IIR/FIR and N-path filters using a novel switched-capacitor technique

Using novel SC (switched-capacitor) differentiators and the synthetic division technique, discrete-time IIR and FIR (infinite- and finite-impulse-response) transfer functions have been realized by sample-data SC analog circuits. The resulting filter structures are simple, compact, and stray-insensitive. Moreover, they have a low component sensitivity, good low-frequency noise performance, and large enough dynamic range. Theoretical calculation and SWITCAP simulation results on certain types of filters have shown good consistency with the experimental results, which substantiates both the design methodology and the circuit functions. The multiplexing technique can be directly applied to the SC differentiators without modification. Thus the multiplex differentiators can be used to design filter banks, which may save chip area and reduce DC power dissipation. Circuit examples are given, and their functions are successfully verified through chip fabrication and measurement. The multiplexed SC differentiators are modified to form three types of N-path circuits, which can be used to design a narrowband bandpass filter. Because the N-path circuits are based on SC differentiators rather than SC integrators, they have a distinct performance superiority to SC integrator-based N-path circuits. >

Realizations of IIR/FIR and N-path filters using a novel switched-capacitor technique

Using novel SC (switched-capacitor) differentiators and the synthetic division technique, discrete-time IIR and FIR (infinite- and finite-impulse-response) transfer functions have been realized by sample-data SC analog circuits. The resulting filter structures are simple, compact, and stray-insensitive. Moreover, they have a low component sensitivity, good low-frequency noise performance, and large enough dynamic range. Theoretical calculation and SWITCAP simulation results on certain types of filters have shown good consistency with the experimental results, which substantiates both the design methodology and the circuit functions. The multiplexing technique can be directly applied to the SC differentiators without modification. Thus the multiplex differentiators can be used to design filter banks, which may save chip area and reduce DC power dissipation. Circuit examples are given, and their functions are successfully verified through chip fabrication and measurement. The multiplexed SC differentiators are modified to form three types of N-path circuits, which can be used to design a narrowband bandpass filter. Because the N-path circuits are based on SC differentiators rather than SC integrators, they have a distinct performance superiority to SC integrator-based N-path circuits. >

Theory and applications of all-digital N-path filters

The all-digital N -path filter structure for the processing of discrete-time signals is introduced. The structure is made of N parallel paths having identical time-invariant digital filters. The filters are connected to a common input signal path through input modulators, and a common output signal path through output modulators. The modulators produce identical periodic sequences but are staggered in phase from filter to filter. A detailed time-domain and frequency-domain analysis of the N -path filter is provided. It is shown that for certain bandlimited modulating sequences, or by appropriately bandlimiting the input and output signals, the overall time-varying structure can be made to appear as a timeinvariant network. This approach leads to filters with adjustable characteristics, and it is shown that by time-sharing the time-invariant digital filter path N times, it is possible to design filters with complex characteristics quite economically. A number of useful modulating functions are described, and some possible applications are discussed.

An integrated six-path wave-SC filter

Experimental results of a switched capacitor (SC) N-path filter integrated in a CMOS Si-gate technology are reported, with N=6. The circuit is based on the theory of wave-flow networks and uses only fully stray-eliminating (usually referred to as stray-insensitive) SC amplifier and integrator circuits. The two main drawbacks of N-path filters, i.e. unwanted mirror frequencies due to path mismatch and clock feedthrough located in the passbands, as solved by multiplexing large filter parts and by using a third-order high-pass reference filter, respectively. The integrated six-path filter features low power consumption due to the use of dynamic amplifiers.