N-metal Oxide Semiconductor Research Articles

Integrated 2T1C pixel circuit with a-Si TFT and NMOS for active matrix mini-LED displays

The 2T1C pixel driver circuit for mini-LED direct display has been proposed, which separates the switching transistor and the driver transistor from the same display substrate, replaces the driver transistor with n-metal oxide semiconductor (NMOS), and combines printed circuit board substrate and thin-film transistor (TFT) substrate to improve the driving capability of the circuit. The NMOS was soldered with mini-LEDs simultaneously onto a substrate which connects to the a-Si TFT array. Two driving modes for a 32-level gray-scale display panel were investigated to compare the voltage-current and optical characteristics. The results demonstrated that the drain-driving mode is better suited for high brightness and high-power display application scenarios as it supports higher-driven currents, but the source-driving mode is more appropriate for precision gray-scale applications due to the higher current linearity of the mode.

Work Function Estimation of Gallium-Doped Zinc Oxide Using Transparent Gate Electrode MOSFET

In this research, the work function (WF) of RF sputtered GZO thin films has been estimated using the electrical characteristics n-Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) device. Two identical sets of MOSFETs were fabricated in this work using a four-level mask. These MOSFETs have two different types of gate contact materials (Al and GZO respectively). GZO was deposited by using RF magnetron sputtering technique while Al was deposited using the thermal evaporation technique. By comparison of the work function of the two MOSFETs, the work function of RF sputtered GZO thin films was identified to be around 4.58 eV.

Work Function Extraction of Transparent Conducting Indium Oxide Films Used As Gate Electrode for MOSFET

Indium Oxide (In2O3) has received a great deal of attention recently as a transparent conducting oxide (TCO) semiconductor that finds applications in photovoltaic solar cells, transparent windows [1] and flat panel displays due to its high electrical conductivity and good optical transparency in the visible region [2]. It is critical to understand the work function (WF) of a material since it is an important characteristic which has an impact on the device performance.In this work, WF of In2O3 has been estimated by fabricating n-Metal Oxide Semiconductor Field Effect Transistor (NMOSFET). Fabrication of two MOSFET devices has been carried out using four-level mask. The source and drain contacts for both the devices have been prepared by using Aluminum metal. The gate contact for one of the MOSFET devices was prepared using Aluminum metal and transparent conducting In2O3 is used as the gate contact for the second MOSFET. Aluminum deposition was carried out using thermal evaporation technique. A 2-inch copper-backed indium target is used to deposit thin films of In2O3 by RF magnetron sputtering and varying the oxygen gas flow. The substrate temperature is held constant at room temperature. Electrical characterization is performed on the fabricated MOSFETs which is further used in extracting the WF of In2O3 thin films. Timo Jäger, Yaroslav E. Romanyuk, Shiro Nishiwaki, Benjamin Bissig, Fabian Pianezzi, Peter Fuchs, Christina Gretener, Max Döbeli, and Ayodhya N. Tiwari , "Hydrogenated indium oxide window layers for high-efficiency Cu(In,Ga)Se2 solar cells" , Journal of Applied Physics 117, 205301 (2015)Min-Suk Lee, Won Chel Choi, Eun Kyu Kim, Chun Keun Kim, Suk-Ki Min, Characterization of the oxidized indium thin films with thermal oxidation, Thin Solid Films, Volume 279, Issues 1–2, 1996, Pages 1-3, ISSN 0040-6090.

Work Function Extraction of Transparent Conducting Indium Oxide Films Used As Gate Electrode for MOSFET

In this work, work function of In2O3 has been estimated by fabricating n-Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) device. Two types of MOSFET devices has been fabricated using a four-level mask. Aluminum (Al) deposited using thermal evaporation was used as the gate contact for one type of MOSFET whereas transparent conducting In2O3 fabricated using RF magnetron sputtering technique was used as the gate contact metal for the second type of MOSFET. Work function of In2O3 was extracted by electrical characterization of the MOSFET devices. The average work function of In2O3 thin films was calculated to be 4.21 eV.

A C-band low-power sub-1volt current-reused multiphase oscillator

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.

Large-area (64 × 64 array) inkjet-printed high-performance metal oxide bilayer heterojunction thin film transistors and n-metal-oxide-semiconductor (NMOS) inverters

It is a big challenge to construct large-scale, high-resolution and high-performance inkjet-printed metal oxide thin film transistor (TFT) arrays with independent gates for the new printed displays. Here, a self-confined inkjet printing technology has been developed to construct large-area (64 × 64 array), high-resolution and high-performance metal oxide bilayer (In2O3/IGZO) heterojunction TFTs with independent bottom gates on transparent glass substrates. Inkjet printing In2O3 dot arrays with the diameters from 55 to 70 μm and the thickness of ∼10 nm were firstly deposited on UV/ozone treated AlOx dielectric layers, and then IGZO dots were selectively printed on the top of In2O3 dots by self-confined technology to form In2O3/IGZO heterojunction channels. When the inkjet-printed IO layers treated by UV/ozone for more than 30 min or oxygen plasma for 5 min prior to print IGZO thin films, the mobility of the resulting printed In2O3/IGZO heterojunction TFTs are correspondingly enhanced to be 18.80 and 28.44 cm2 V−1 s−1 with excellent on/off ratios (>108) and negligible hysteresis. Furthermore, the printed N-Metal-Oxide-Semiconductor (NMOS) inverter consisted of an In2O3/IGZO TFT and an IGZO TFT has been demonstrated, which show excellent performance with the voltage gain up to 112. The strategy demonstrated here can be considered as general approaches to realize a new generation of high-performance printed logic gates, circuits and display driving circuits.

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct-current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is −114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm2 including the bond pads.

Silicon nanowire ratioed inverters on bendable substrates

In this study, we demonstrate the performance of silicon nanowire (SiNW)n-metal oxide semiconductor (MOS) and p-MOS ratioed inverters that are fabricated on bendable substrates. The electrical characteristics of the fabricateddevices can be controlled by adjusting the load voltage. The logic swings of then- and p-MOS ratioed inverters at a low supply voltage of 1 V are 80% and 96%, respectively. The output voltage level of the p-MOS ratioed inverter is close to rail-to-rail operation. The device also exhibits stable characteristics with goodfatigue properties. Our bendable SiNW ratioed inverters show promise asa candidate building block for future bendable electronics.

Design of miniaturised on‐chip slot antenna for THz detector in CMOS

For the miniaturisation of the terahertz detector with on-chip antenna, the slotted patch antennas in different shape are studied. Through analysing and comparing of the antennas in rectangle, circular and diamond shape, with and without slot, the double arc slots and diagonal slots are proposed for the circular patch antenna and the diamond patch antenna, respectively, which can increase the current path to reduce the size of the patch antenna effectively. The optimised radius of the circular patch antenna is 130 μm and the diagonal of the diamond patch antenna is 207.2 μm, whose size is reduced about 12 and 40%, respectively. Fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm standard complementary metal oxide semiconductor (CMOS) process, the N Metal Oxide Semiconductor (NMOS) detector with proposed antenna has the response frequency ranging from 270 to 320 GHz. For the detector 1 with circular antenna and detector 2 with diamond antenna, the maximum response voltage is 419 and 110 μV at the frequency of 290 and 280 GHz, respectively.

A highly linear RF mixer using gate-all-around junctionless transistor

ABSTRACTIn this paper, we investigate the performance of a radio-frequency (RF) mixer based on single-silicon nanowire gate-all-around (GAA) junctionless field-effect transistor (JLFET). The main novelty in this work is the achievement of high linearity of RF mixer using band-to-band tunnelling phenomenon of GAA-JLFET. Using technology computer-aided design (TCAD) simulations, we extracted the value of unity-gain cut-off frequency of 420 GHz, which shows its potential for circuit applications in the extremely high-frequency regime. The harmonic-balanced simulations in Agilent advanced design system tool with an emphasis on the device-circuit interaction are used to analyse the RF mixer performance, such as output spectrum, 1-dB compression point, and conversion gain in comparison with 32-nm conventional n-metal oxide semiconductor transistor.

Fabrication of Advanced High-Speed Complementary Metal Oxide Semiconductor Field Effect Transistor

In this study we propose the fabrication of advanced high-speed complementary metal oxide semiconductor field effect transistor (AHCMOS) by combining a P-carbon nanotube with n-metal oxide semiconductor (NMOS) on a single chip. The target is to achieve extremely high speed low-power dissipating miniaturized device with improved functionalities.  The technology of conventional metal oxide semiconductor field effect transistor (MOSFET) and nanotechnology are applied in this research. A P-carbon nanotube is complemented with the conventional NMOS all embedded on the same chip.  Although it is possible to fabricate both a P and N carbon nanotube to form a complementary pair, and also a PMOS and NMOS to form a complementary pair, however in this research we propose a hybrid structure with carbon nanotube transistor technology and complementary MOSFET technology. This device therefore combines the best characteristics of carbon nanotube technology and CMOS technology to provide enhanced logic functions that are optimized for the high-speed, low-power systems and miniaturized size ideal for very large scale integration (VLSI).

The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (Vt) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2 interface during forming gas anneal together with low O concentration in the TiN enables low NMOS Vt. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS Vt.

The modulation effect of substrate doping on multi-node charge collection and single-event transient propagation in 90-nm bulk complementary metal-oxide semiconductor technology

Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor (CMOS) technologies, which are significant for charge sharing, thus affecting the propagated single event transient pulsewidths in circuits. The trends of charge collected by the drain of a positive channel metal-oxide semiconductor (PMOS) and an N metal-oxide semiconductor (NMOS) are opposite as the substrate doping increases. The PMOS source will inject carriers after strike and the amount of charge injected will increase as the substrate doping increases, whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough. Additionally, it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current, and has little effect on the drift and diffusion. The change in substrate doping has a much greater effect on PMOS than on NMOS.

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal–oxide–semiconductor field-effect transistor (nMOSFETs). In this research, molecular carbon (C) ion implantation and recrystallization schemes employed to achieve strained Si:C films with a high substitutionally incorporated carbon concentration ([C]sub) and a high ratio of substitution were studied. Several recrystallization techniques including rapid-thermal-annealing (RTA)-based solid phase epitaxy (SPE), spike annealing, and nonmelt laser annealing have been used to optimize C incorporation into Si and strain application. Results of these different implantation and annealing techniques are compared and discussed. Furthermore, we proposed the first recrystallization by nonmelt laser annealing and the co-incorporation of a dopant that increases the rate of Si regrowth and has a covalent radius slightly different from that of Si. These processes markedly promoted the recrystallization of C densely incorporated in an amorphous Si layer and improved the crystallinity of strained Si:C films while maintaining a high [C]sub at a high ratio of substitution.

Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator

The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicon-on-insulator (SOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to 1.4 ×1017 cm-3 and then decreases with higher doping concentrations. In particular, at a concentration of 1.4 ×1017 cm-3 it increased 1.8 times compared with that at 1.5 ×1015 cm-3. This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.

Effect of nitrogen implantation at the SiO2/SiC interface on the electron mobility and free carrier density in 4H-SiC metal oxide semiconductor field effect transistor channel

The electrical characteristics of n-metal oxide semiconductor field effect transistors (n-MOSFETs) fabricated on 4H-SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface. A strong correlation among the increase in the N concentration, the reduction of the interface state density near the conduction band and the improvement of the MOSFET performance was obtained. Hall-effect measurements were used to determine the electron mobility and the free carrier concentration in the MOSFET channel. Among the investigated combinations of N dose and oxidation time, the one with the higher dose and the shorter time produces MOSFETs with the higher N concentration at the SiO2/SiC interface and the best electrical characteristics. This superior performance is obtained in spite of the lowering of the bulk mobility in the channel of this sample, a negative effect probably ascribable to the incomplete recovery of the implantation damage or to the high density of interstitial nitrogen atoms present in the channel region. However, evidence of extended defects, clusters or nanoparticles was not observed by transmission electron microscopy analyses in any of the investigated SiC MOSFET devices.

Elastic relaxation in patterned and implanted strained silicon on insulator

Mechanical relaxations of strained silicon on insulator (sSOI) nanostructures are studied for the isolation and implantation processes used in transistor technology. Two model systems are quantitatively analyzed by grazing incidence x-ray diffraction: long etched sSOI lines of different widths and bidimensional (2D) sSi samples implanted by As/Xe ions with the same stripe geometry, the gate stack acting as an implantation mask. For sSOI lines, the strain of the initial 2D layer is conserved along the longer direction, i.e., the transport direction. Along the small direction, a large relaxation is observed especially for the smaller widths. This relaxation is almost complete for thicker samples (70 nm), whereas it is much more limited for thinner ones (10 nm). The tuning by etching/size selection of the sSOI initial biaxial stress into uniaxial stress along the transport direction should represent a great advantage for n-metal oxide semiconductor (n-MOS) devices in terms of mobility. Similar relaxation anisotropies have been observed for the implanted samples with 60 nm thickness. In this case, the relaxed small dimension of the area under the gate stack corresponds to the transport direction. This direct source/drain implantation step should therefore damage the performance of partially depleted sSOI n-MOS devices. However these relaxation phenomena should be advantageously used with new integration schemes.

Comparative study of self-heating effect on electron mobility in nano-scale strained silicon-on-insulator and strained silicon grown on relaxed SiGe-on-insulator n-metal–oxide–semiconductor field-effect transistors

From the viewpoint of the silicon thickness limit for mobility enhancement in a strained Si channel, we investigated the difference in the self-heating effect on electron mobility between strained silicon-on-insulator (sSOI) and strained Si grown on relaxed SiGe-on-insulator (ε-Si SGOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) as a function of silicon thickness. We found, for the first time, by numerical simulation that when considered with the presence of self-heating in the silicon thickness range from 5 to 10 nm, the reduction in the mobility enhancement ratio of sSOI n-MOSFETs is less than that of ε-Si SGOI n-MOSFETs by numerical simulation. In addition, we confirmed that the quantum size effect, occurring at the peak mobility value of a 3 nm silicon thickness, disappeared in sSOI n-MOSFETs but was suppressed in ε-Si SGOI n-MOSFETs. Therefore, we propose that an sSOI n-MOSFET is a more promising device than a ε-Si SGOI n-MOSFET for high-performance devices with a design rule of less than 45 nm.

Hot carrier degradation in HfSiON∕TiN fin shaped field effect transistor with different substrate orientations

Hot carrier injection (HCI) degradation is evaluated for n-metal oxide semiconductor (MOS) and pMOS high-κ-fin shaped field effect transistor with (100) and (110) sidewall surface orientations. It was found that impact ionization at the source, in addition to the traditional drain side enhances HCI degradation for the Vg=Vd condition. The degradation increases with decreasing fin length, with negligible dependence on substrate orientation.