N-channel Junction Field-effect Transistors Research Articles

A silicon carbide high gain differential amplifier for extreme temperature applications

In this paper, a high temperature, high gain differential amplifier based on a custom-built silicon carbide (SiC) N-channel junction field effect transistor (JFET) only, without using complementary P-channel devices is proposed. The operation principle of this active load differential amplifier is discussed, and the expression of the differential gain is derived. A prototype circuit is fabricated using thick film process on an alumina substrate and tested from room temperature up to 500 °C to demonstrate the high temperature capability of the proposed differential amplifier. The differential gain of 50.8 dB is achieved with 58.6 dB common-mode rejection ratio (CMRR) and 9.1 MHz gain bandwidth product (GBW) at 500 °C. Excellent linearity and low output impedance of the proposed differential amplifier are also demonstrated at various temperatures. The proposed SiC JFET high gain differential amplifier can serve as a fundamental building block of the signal conditioning circuitry to be integrated with the sensing element for extreme environment applications.

SiC Complementary Junction Field-Effect Transistor Logic Gate Operation at 623 K

Here, we show that silicon carbide (SiC) complementary logic gates composed of p- and n-channel junction field-effect transistors (JFETs) fabricated by ion implantation operate at 623 K with a supply voltage as low as 1.4 V. The logic threshold voltage shift of the complementary JFET (CJFET) inverter is only 0.2 V from 300 to 623 K. Furthermore, temperature dependencies of the static and dynamic characteristics of the CJFET inverter are well explained by a simple analytical model of SiC JFETs.

High-Performance van der Waals Junction Field-Effect Transistors Utilizing Organic Molecule/Transition Metal Dichalcogenide Interface.

Two-dimensional (2D) transition metal dichalcogenide (TMD) hetero PN junctions with a van der Waals (vdW) interface have received much attention, because PN diodes are basically important to control the vertical current across the junction. Interestingly, the same vdW PN junction structure can be utilized for junction field-effect transistors (JFETs) where in-plane current is controlled along the junction. However, 2D vdW JFETs seem rarely reported, despite their own advantages to achieve when good vdW junction is secured. Here, we present high-performance p-MoTe2 JFETs using almost perfect vdW organic Alq3/p-MoTe2 junctions and demonstrate organic NPB/n-MoS2 JFETs. The p- and n-channel JFETs stably show high mobilities of 60-80 and ∼800 cm2/V s, respectively, along with a high ON/OFF current ratio (>1 × 105) and minimal gate leakage at 5 V even after a few months. Such performances are attributed to a quality vdW junction at organic layer/TMD interfaces.

Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors operational at 400 °C* *Project supported by the Key Research and Development Program of Shaanxi Province, China (Grant No. 2020ZDLGY03-07), the National Science Foundation of China (Grant Nos. 61774117 and 61774119), the Science Challenge Project (Grant No. TZ2018003), the National Key R&D Program of China (Grant No. 2017YFB0102302), the Shaanxi Science & Technology

This paper presents the development of lateral depletion-mode n-channel 4H-SiC junction field-effect transistors (LJFETs) using double-mesa process toward high-temperature integrated circuit (IC) applications. At room temperature, the fabricated LJFETs show a drain-to-source saturation current of 23.03 μA/μm, which corresponds to a current density of 7678 A/cm2. The gate-to-source parasitic resistance of 17.56 kΩ ⋅ μm is reduced to contribute only 13.49% of the on-resistance of 130.15 kΩ ⋅ μm, which helps to improve the transconductance up to 8.61 μS/μm. High temperature characteristics of LJFETs were performed from room temperature to 400 °C. At temperatures up to 400 °C in air, it is observed that the fabricated LJFETs still show normally-on operating characteristics. The drain-to-source saturation current, transconductance and intrinsic gain at 400 °C are 7.47 μA/μm, 2.35 μS/μm and 41.35, respectively. These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.

Technological and devices modeling of complementary JFETs over a wide temperature range

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the “freezing out” of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range ΔT = 150–330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range ΔT = 150–77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

High-performance junction field-effect transistor based on black phosphorus/β-Ga2O3 heterostructure

Black phosphorous (BP), an excellent two-dimensional (2D) monoelemental layered p-type semiconductor material with high carrier mobility and thickness-dependent tunable direct bandgap structure, has been widely applied in various devices. As the essential building blocks for modern electronic and optoelectronic devices, high quality PN junctions based on semiconductors have attracted widespread attention. Herein, we report a junction field-effect transistor (JFET) by integrating narrow-gap p-type BP and ultra-wide gap n-type β-Ga2O3 nanoflakes for the first time. BP and β-Ga2O3 form a vertical van der Waals (vdW) heterostructure by mechanically exfoliated method. The BP/β-Ga2O3 vdW heterostructure exhibits remarkable PN diode rectifying characteristics with a high rectifying ratio about 107 and a low reverse current around pA. More interestingly, by using the BP as the gate and β-Ga2O3 as the channel, the BP/β-Ga2O3 JFET devices demonstrate excellent n-channel JFET characteristics with the on/off ratio as high as 107, gate leakage current around as low as pA, maximum transconductance (gm) up to 25.3 µS and saturation drain current (IDSS) of 16.5 µA/µm. Moreover, it has a pinch-off voltage of –20 V and a minimum subthreshold swing of 260 mV/dec. These excellent n-channel JFET characteristics will expand the application of BP in future nanoelectronic devices.

SnSe/MoS2 van der Waals Heterostructure Junction Field-Effect Transistors with Nearly Ideal Subthreshold Slope.

The minimization of the subthreshold swing (SS) in transistors is essential for low-voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal-oxide-semiconductor field-effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec-1 at room temperature). However, another type of transistor, the junction field-effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS2 van der Waals (vdW) heterostructure-based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS2 vdW heterostructure exhibits excellent p-n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS2 as the channel, the SnSe/MoS2 vdW heterostructure exhibit well-behavioured n-channel JFET characteristics with a small pinch-off voltage VP of -0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec-1 and high ON/OFF ratio over 106 , demonstrating excellent electronic performance especially in the subthreshold regime.

Van der Waals junction field effect transistors with both n- and p-channel transition metal dichalcogenides

Two-dimensional (2D) transition metal dichalcogenides (TMDs)-based van der Waals (vdW) PN junctions have been used for heterojunction diodes, which basically utilize out-of-plane current across the junction interface. In fact, the same vdW PN junction structure can be utilized for another important device application, junction field effect transistors (JFETs), where in-plane current is possible along with 2D–2D heterojunction interface. Moreover, the 2D TMD-based JFET can use both p- and n-channel for low voltage operation, which might be its unique feature. Here we report vdW JFETs as an in-plane current device with heterojunction between semiconducting p- and n-TMDs. Since this vdW JFET would have low-density traps at the vdW interface unlike 2D TMD-based metal insulator semiconductor field effect transistors (MISFETs), little hysteresis of 0.0–0.1 V and best subthreshold swing of ~100 mV/dec were achieved. Easy saturation was observed either from n-channel or p-channel JFET as another advantage over 2D MISFETs, exhibiting early pinch-off at ~1 V. Operational gate voltage for threshold was near 0 V and our highest mobility reaches to ~>500 cm2/V·s for n-channel JFET with MoS2 channel. For 1 V JFET operation, our best ON/OFF current ratio was observed to be ~104.

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25- $\mu \text{m}$ bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage ( ${V} _{P}$ ) and the zero-bias drain current ( ${I} _{{\mathsf {DS0}}}$ ) of the proposed n-JFET device can be modified by adjusting the P+ separation ( $L$ ) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ${I} _{D}$ – ${V} _{D}$ and ${I} _{D}$ – ${V} _{G}$ .

Research and development of a high-performance differential-hybrid charge sensitive preamplifier

A differential-hybrid charge sensitive preamplifier (CSP) was designed by taking a monolithic dual N-Channel Junction Field-effect Transistor (JFET) and a high-speed, low-noise, operational amplifier as the core parts. Input-stage of the circuit employs low-noise differential dual JFET, which ensures high input impedance and low noise. The differential dual transistor makes the quiescent point of the first-stage differential output stable, which is convenient for connecting with the post stage high-speed operational amplifier. Broadband could be amplified by connecting to the double differential dual transistors through the folded cascode-bootstrap. The amplifying circuit which replaces the interstage and post stage discrete components of a traditional CSP with integrated operational amplifier is simpler and more reliable. It simplifies the design of the quiescent point, gives full play to advantages of releasing large open-loop gain, and improves charge-voltage conversion gain stability. Particularly, the charge-voltage conversion gain is larger under a smaller feedback capacitor, thus enabling to gain better signal-noise ratio. The designed CSP was tested, reporting 3.3×1013 V/C charge sensitivity, about 90ns rise time of signals, 35:1 signal-noise ratio to gamma-rays of 137Cs (662keV) and a 0.023 fC/pF noise slope. Gamma-rays of 241Am (59.5keV) were measured by the BPX66 detector and the designed CSP under room temperature, providing 1.97% energy resolution.

Modeling Statistical Dopant Fluctuations Effect on Threshold Voltage of Scaled JFET Devices

This paper presents a simple mathematical expression to model the effect of statistical dopant fluctuations on threshold voltage ( $V_{th}$ ) of junction field-effect transistors (JFETs). The random discrete doping (RDD) in the active device area is used to derive an analytical model to compute the standard deviation, $\sigma V_{th,RDD}$ of the $V_{th}$ -distribution for any arbitrary channel doping profiles. The model shows that the $V_{th}$ -variability in JFETs depends on the active device area, channel doping concentration, and the depth of the channel depletion region of the gate/channel $pn$ -junction. The model is applied to compute $\sigma V_{th,RDD}$ for symmetric and asymmetric source/drain double-gate n-channel JFETs. The simulation results show that the model can be used for predicting $V_{th}$ -variability in JFETs.

4H-SiC N-Channel JFET for Operation in High-Temperature Environments

Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors (JFETs) are demonstrated to operate with well-behaved electrical characteristics at temperatures up to 600 °C in air. Ti/Ni/TiW metal stacks are used to form ohmic contacts to n-type 4H-SiC with specific contact resistance of \(1.14 \times 10^{-3}~{\boldsymbol{\Omega }}\) cm \(^{2 }\) at 600 °C. The on/off drain saturation current ratio and intrinsic gain at 600 °C are \(1.53 \times 10^{3}\) and 57.2, respectively. These results indicate that 4H-SiC JFETs can be used for extremely-high-temperature electronics applications.

Electrostatics of JFET at 6 nm channel length: a simulation study

A junction field effect transistor (JFET) is studies as an alternative device for performing complementary logic currently limited to MOS. Complementary logic with cJFET bult using 60 nm lithography was reported recently. This summarises the simulation results of scaled n-channel JFET with a gate length of 6 nm. The JFET was operated in double gate mode. Results of this simulation study reveal that it is possible to scale JFET gate length to 6 nm operating at 0.5 V and achieve an ion/loff ratio greater than 5000. Threshold voltage can be varied by varying the channel profile. In Essence, JFET needs to be considered as a viable candidate for future scaling.

Silicon Mach-Zehnder Waveguide Interferometer on Silicon-on-Silicon (SOS) Substrate Incorporating the Integrated Three-Terminal Field-Effect Device as an Optical Signal Modulation Structure

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550nm. The three different modulation lengths (ML) of 500, 1000, and 2000µm while keeping the overall MZI length constant at 1.5cm were set as a general design rule for these 10µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50mA current (Is) to achieve a π phase shift, the modulation efficiency of the device was measured to be η =π/(Is·L) $\\simeq$ 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5µsec and the 3dB roll-off frequency (f3dB) measured was in the excess of ∼400kHz.

A New High Performance Realization of Hyperchaotic Modified Canonical Chua Circuit Using JFETs

A new implementation of hyperchaotic modified canonical Chua circuit using junction field-effect transistors (JFETs) is proposed. The design is based on a source coupled JFET circuit to approximate a smooth cubic non-linearity and a two-terminal negative resistance element containing a p-n-p silicon transistor and an n-channel JFET. The realization is supported by Orcad Pspice simulation and numerical MATLAB results. The hyper-chaotic nature is confirmed by two positive Lyapunov exponents associated with the attractor which is a fractal with a Lyapunov dimension between 3 and 4.

Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor

In this letter, a novel type of high-voltage n-channel junction field-effect transistor (JFET) was designed using a conventional n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) without changing any step in the process. High-voltage JFET can be a start-up device in power factor correction, dc-ac converters, and ac-dc converters for providing a self-powered circuit and minimizing standby power losses without gate control because of its negative threshold voltage. Experimental results show that an n-LDMOS with this JFET structure can achieve a reverse blocking voltage of more than 700 V with very low leakage current. The pinch-off voltage can be designed by changing n-well width to meet the circuit requirement.

Low Noise Junction Field Effect Transistors in a Silicon Radiation Detector Technology

We report on n-channel Junction Field Effect Transistors fabricated on high resistivity silicon by means of a specially tailored radiation detector technology. This research activity is being carried out in the framework of a project aiming at the integration of read-out circuits in the same detector substrate. Possible applications are in the field of medical/industrial imaging, space and high energy physics experiments. The pre-existent fabrication process has been modified in several respects to enhance the device noise behavior. In particular, the new process features a high-energy (1 MeV) Boron implantation to obtain a deep p-well which ensures an effective isolation of the transistor from the substrate and a strong modulating effect on the current. Selected results from the experimental characterization of transistors and charge sensitive amplifiers are presented, showing a sizable enhancement in the noise performance with respect to previously available devices

Measurement of Low-Frequency Noise of Modern Low-Noise Junction Field Effect Transistors

A description of the low-noise measurement system designed for experimental investigation of low-frequency noise of modern low-noise junction field effect transistors (JFETs) at a frequency range from 0.5 Hz to 50 kHz is presented. The noise floor of the system in terms of noise voltage spectral density is about 1.3 nV//spl radic/Hz at frequency 0.5 Hz, 0.6 nV//spl radic/Hz at frequency 1 Hz, 0.08 nV//spl radic/Hz at frequency 10 Hz, and /spl les/0.04 nV//spl radic/Hz at frequencies 100 Hz-50 kHz. Such a system makes it possible to measure 1/f noise and channel thermal noise of modern very low noise n-channel JFETs. Specifically, discrete samples of JFETs, IF9030, IF1801, IF3601, and 2N4338, were investigated at the frequency range mentioned above. The system provided negligible contribution of all noise sources except intrinsic noise of measured JFETs which was a 1/f noise at frequencies f < 10 Hz and a channel thermal noise at frequencies f /spl ges/ 10 Hz. The measured values of the equivalent input noise voltage spectral density e/sub n/ of the best samples from investigated JFETs IF9030, IF1801, IF3601, and 2N4338 were 2.7, 3.2, 3.4, and 22 nV//spl radic/Hz at frequency 0.5 Hz; 1.5, 2.1, 1.8, and 14 nV//spl radic/Hz at frequency 1 Hz; and 0.5, 0.4, 0.6, and 3.2 nV//spl radic/Hz at frequencies more than 1 kHz, correspondingly.

Proton-induced damage in JFET transistors and charge preamplifiers on high-resistivity silicon

The results discussed in this paper are relevant to junction field effect transistors (JFETs) and JFET-based charge sensitive amplifiers fabricated in a detector compatible process. Such structures were irradiated with 27 MeV protons to evaluate the suitability of the technology for space applications and high-energy physics experiments from the standpoint of radiation tolerance. The process investigated in this work, originally designed for the fabrication of silicon detectors to be operated in a fully depleted condition, has been tuned to embed N-channel JFETs, NMOS devices and bipolar transistors in the same high resistivity substrate. The most significant electrical parameters have been monitored after exposing the test structures to different proton fluences in order to characterize their total dose and bulk damage response. Comparison with the results from previous irradiations with /spl gamma/-rays might be helpful in shedding light on the fundamental mechanisms underlying radiation damage in JFET silicon devices.