A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

Abstract

A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25- $\mu \text{m}$ bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage ( ${V} _{P}$ ) and the zero-bias drain current ( ${I} _{{\mathsf {DS0}}}$ ) of the proposed n-JFET device can be modified by adjusting the P+ separation ( $L$ ) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ${I} _{D}$ – ${V} _{D}$ and ${I} _{D}$ – ${V} _{G}$ .