mW Power Consumption Research Articles

A heterogenous integrated neural recording system with elastocapillary self-assembled Au-PDMS-PEG neural probe and customized ASIC

Abstract This study presents the design and implementation of a heterogenous integrated neural recording system consisting of a flexible Au-PDMS-PEG probe and customized complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) in a standard 0.18 μm process. The flexible Au-PDMS-PEG probe was prepared by an elastocapillary self-assembled process, achieving an electrode impedance of 250 kΩ (@1 kHz). The customized CMOS ASIC contains 36 modular digital pixels (MDP). It achieves 5.69 μVrms input referred noise, 10.29 effective number of bits, 49.5 μW power consumption, and 0.092 mm2 area for a single MDP unit. Spontaneous spikes were also recorded in the mouse cortex, with a peak-to-peak amplitude of 389.2 μVPP and a signal-to-noise ratio of 19.36. Benchtop and in-vivo experiments were conducted to validate the functionality and performance of the proposed neural recording system.

A 10-bit 70-MS/s SAR ADC with Reference Buffer in 40nm CMOS

Abstract A 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with reference buffer is presented in this paper. Segmented capacitive DAC with redundant 2bits is designed to relax the design of reference buffer. A hybrid switching sequence is applied to the ADC to optimize power consumption. The Measurement results Show that the core SAR ADC achieves 48.52 dB SNDR and 56.67 dB SFDR at 70 MS/s sampling rate and Nyquist input frequency, consuming 2.50mW power consumption, achieving a FoM of 163.6 fJ/step. The ADC occupies an active area of 0.017 mm2 in 40nm CMOS technology.

A Novel Instruction Driven 1-D CNN Processor for ECG Classification.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively.

A 16-channel Si probe monolithically integrated with CMOS chips for neural recording

Multi-channel neural electrodes as a crucial means are of great significance for information exchange between the brain and computers. Herein, we present a 16-channel Si-based active neural probe system that achieves a monolithic integration between the electrodes and circuits in a single probe, making it a standalone integrated electrophysiology recording system. The ASIC prepared on a base (2×2mm2) is a 16-channel analog frontend (AFE) for neural recording, and each channel has a low-noise amplifier (LNA), a bandpass filter (BPF), a buffer and a current bias circuit. The 258 neural signal recording electrodes (22×24μm2) are densely packed on a 50 μm thick, 100 μm wide, and 3 mm long shank. The ASIC of neural probe, internal interconnecting wires are all implemented in commercial SMIC 0.18 μm CMOS technology. The neural probe system achieves a 3.6 μVrms input-referred noise (IRN) in a bandwidth of 1.1Hz-10 kHz, 70.8 μW power consumption, 0.0785 mm2 area per channel, as well as an AFE gain of 58.1 dB Furthermore, the impedances of the Au electrodes can be obtained as 0.5–2.1 MΩ at a frequency of 1 kHz. The functionality of a 16-channel silicon-based neural probe is validated in an in-vivo experiment on lab rats.

A Bionic Flapping Magnetic-Dipole Resonator for ELF Cross-Medium Communication.

Extremely low-frequency (ELF) electromagnetic (EM) waves adeptly propagate in harsh cross-medium environments, overcoming rapid decay that hinders high-frequency counterparts. Traditional antennas, however, encounter challenges concerning size, efficiency, and power. Here, drawing inspiration from nature, we present a groundbreaking piezo-actuated, bionic flapping-wing magnetic-dipole resonator (BFW-MDR), operating in the electro-mechano-magnetic coupling mechanism, designed for efficient ELF EM wave transmission. The unique rigid-flexible hybrid flapping-wing structure magnifies rotation angles of anti-phase magnetic dipoles by tenfold, leading to constructive superposition of emitted magnetic fields. Consequently, the BFW-MDR exhibits a remarkable quality factor of 288 and an enhanced magnetic field emission of 514 fT at 100 meters with only 6.9 mW power consumption, surpassing traditional coil antennas by three orders of magnitude. The communication rate is doubled by the ASK+PSK modulation method. Its robust performance in cross-medium communication, even amidst various interferences, underscores its potential as a highly efficient antenna for underwater and underground applications.

Low-power body-coupled transceiver for miniaturized body area networks

As wearable devices continue to proliferate, seamlessly integrating them into wireless body-area networks (WBANs) becomes increasingly crucial. Body-coupled communication (BCC) emerges as a promising WBAN technology, utilizing the human body itself as a transmission channel. This paper presents a novel BCC transceiver designed for efficiency and miniaturization. The proposed transceiver prioritizes reliable data transmission with a convolutional encoder. It leverages a simple direct digital synthesizer (DDS) for frequency shift keying (FSK) modulation, minimizing chip area. At the receiver, a Viterbi decoder (VD) ensures accurate data recovery. This design shines in its resource efficiency. It occupies less than 1% of an Artix-7 FPGA, operates at 268.77 MHz with a mere 111 mW power consumption, and achieves a remarkable data rate of 13.78 Mbps. This translates to a hardware efficiency of 44.46 Kbps/slice, surpassing existing transceivers. Moreover, the BCC transceiver exhibits a stellar bit error rate (BER) of over 10⁻⁷ under realistic body channel conditions. Overall, this work presents a highly efficient BCC transceiver with significant improvements in chip area, power consumption, and data rate compared to existing designs. This paves the way for practical and miniaturized WBAN solutions for future wearable applications.

A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation.

A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.

A High CMRR Differential Difference Amplifier Employing Combined Input Pairs for Neural Signal Recordings.

This article introduces a Combined .symmetrical and complementary Input Pairs (CIP) of a Differential Difference Amplifier (DDA), to boost the total Common-Mode Rejection Ratio (CMRR) for multi-channel neural signal recording. The proposed CIP-DDA employs three input pairs (transconductors). The dc-coupled input neural signal connection, via the gate terminal of the first transconductor, yields a high input impedance. The high-pass corner frequency and dc quiescent operation point are stabilized by the second transconductor. The calibration path of differential-mode gain and Common-Mode Feedback (CMFB) is provided by the proposed third transconductor. The parallel connection has no need for extra voltage headroom of input and output. The proposed CIP-DDA is targeted at integrated circuit realization and designed in a 0.18-μm CMOS technology. The proposed CIP-DDAs with system CMFB achieve an average CMRR of 103 dB, and each channel consumes circa 3.6 μW power consumption.

An area efficient inductorless super-regenerative receiver front-end for biomedical implant devices

Wearable and implantable medical devices are of great importance in diagnosis and treatment as they provide continuous monitoring and data collection. Considering the comfort of the patient and ease-of-operation, these devices require wireless data transmission. In this work, a novel area and energy efficient inductorless super-regenerative receiver (SRR) is proposed for medical implants dedicated to patient monitoring and treatment. The proposed SRR was fabricated in UMC CMOS 180 nm technology. The SRR occupies only 0.072mm2 which corresponds to an order of magnitude area reduction compared to the state-of-the-art. The SRR achieves −70dBm sensitivity and the highest data rate is 4Mbps. 3.22nJ/b energy efficiency is obtained with 12.9mW power consumption from a 1.8V power supply.

A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9[Formula: see text]dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256[Formula: see text]kHz and 312.5[Formula: see text]Hz input with a differential-mode voltage of 700[Formula: see text]mV sinusoidal waveform. Based on SMIC 180[Formula: see text]nm/1.8[Formula: see text]V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52[Formula: see text]dB SNDR, 18.90-bit ENOB, and 8.40[Formula: see text]mW power consumption, which correspond to FoM[Formula: see text] and FoM[Formula: see text] of 0.067[Formula: see text]pJ/step and 163.27[Formula: see text]dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique

This article introduces a compact and low phase noise (PN) 19-GHz quad-core class-F voltage-controlled oscillator (VCO) based on a square-geometry transformer tank using the inductor-sharing technique. The proposed square-geometry transformer tank is inherently more compact than the prevalent topologies such as star geometry, dual-row geometry, and circular geometry. The inductor-sharing technique is introduced to merge neighboring inductors into smaller ones, which further reduces the chip area. Moreover, the proposed quad-core topology supports impedance boosting at harmonic frequencies without extra chip area consumption and class-F operation is adopted to achieve better PN performance. The quad-core VCO prototype is designed and fabricated in a 65-nm CMOS process. Measured performances are 17.6 to 19.4 GHz frequency range with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 137.2 dBc/Hz minimum PN at 10 MHz offset from 19 GHz carrier with 46 mW power consumption and 0.9-V supply, resulting a figure of merit (FoM) of 186.1 dBc/Hz. Thanks to the proposed square-geometry and inductor sharing technique, the proposed VCO is the smallest in quad-core VCOs with a similar operating frequency with a core chip area of 0.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and the corresponding FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{A}}$</tex-math> </inline-formula> is 196.5 dBc/Hz.

A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters.

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications.

Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications

The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a −211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.

Wireless, Multi-Sensor System-on-Chip for pH and Amperometry Powered by Body Heat.

This article presents a body-heat-powered, multi-sensor SoC for measurement of chemical and biological sensors. Our approach combines analog front-end sensor interfaces for voltage- (V-to-I) and current-mode (potentiostat) sensors with a relaxation oscillator (RxO) readout scheme targeting << 10 μW power consumption. The design was implemented as a complete sensor readout system-on-chip, including a low-voltage energy harvester compatible with thermoelectric generation and a near-field wireless transmitter. A prototype IC was fabricated in a 0.18 μm CMOS process as a proof-of-concept. As measured, full-range pH measurement consumes 2.2 μW at maximum, where the RxO consumes 0.7 μW and measured linearity of the readout circuit demonstrates R 2 0.999. Glucose measurement is also demonstrated using an on-chip potentiostat circuit as the input of the RxO, with a readout power consumption as low as 1.4 μ W. As a final proof-of-principle, both pH and glucose measurement are demonstrated while powering from body heat using a centimeter-scale thermoelectric generator on the skin surface, and pH measurement is further demonstrated with an on-chip transmitter for wireless data transmission. Long-term, the presented approach may enable a variety of biological, electrochemical, and physical sensor readout schemes with microwatt operation for batteryless and power autonomous sensor systems.

Study of 18.2-42.0GHz injection-locked frequency doubler with transformer input

This paper presents ultra-wideband 18.2-42.0 GHz LC injection-locked frequency doubler (ILFD) with transformer inputs. To expand the locking range, the proposed ILFD incorporates the transformer connected to the source of the gain-cell transistor to obtain high linearity of the input circuitry, moreover, the input matching frequency shifts from the free-run frequency of the oscillator. The measured maximum locking range exhibited 79.1% from 18.2 GHz to 42.0 GHz output at 0 dBm input power and the locked phase noise at 1MHz offset from 28 GHz carrier frequency was −112.1 dBc/Hz under 1.7 mW power consumption. Also, the lowest locked phase noise at 1 MHz offset from the carrier was −122.8 dBc/Hz under 21.2 mW power consumption, and it was only 2.2 dB degraded from the theoretical value. The process technology used in this work was TSMC-180nm CMOS.

An improved PVT-Robust floating inverter dynamic amplifier for noise-shaping SAR ADCs

The floating inverter dynamic amplifier (FIDA) is a power-efficient, open-loop, and dynamic amplifier without requiring any output common-mode feedback (CMFB) circuit. It is appropriate for low-power applications. However, its gain is not robust over process, voltage, and temperature (PVT) variations. In this work, a simple, low power, and low noise method is proposed to solve this problem. The proposed method controls the amplification time window of the FIDA to be proportional to its time constant. Based on the FIDA gain formula, this technique stabilizes the gain over PVT changes. The proposed PVT-robust FIDA is designed at the circuit level using 0.18 µm TSMC CMOS technology with Cadence Virtuoso tool. According to the post-layout simulation results of a sample design, the gain of the amplifier is 29.4 with 51.3 µW power consumption from a 1.2 V supply voltage. The maximum gain variation over PVT changes is reduced from 49.6% to 9.8% using the proposed gain calibration technique.

A 17 GHz inductorless low‐pass filter based on a quasi‐Sallen–Key approach

SummaryIn this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low‐pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum of about 320 GHz. The biquad has been designed to provide a resonance frequency of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1 Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

Design and Characterization of a Picosecond Timing ASIC in 55-nm CMOS

For more than two decades, amplifier-discriminator ASICs have been demonstrated to be the optimal choice for time measurement in high-energy physics experiments. With the requirement of time resolution further evolving towards the picosecond and sub-picosecond ranges, circuit innovation has become increasingly essential. We present a PIcoSecond Timing (PIST1) ASIC, utilizing the conventional amplifier-discriminator architecture and optimized for the readout of silicon photomultipliers (SiPMs) in the electromagnetic calorimeter (ECAL) for future Higgs factories such as the Circular Electron Positron Collider (CEPC). Further circuit developments are made to enable the ASIC to operate under minimal power with reduced supply voltage. A comprehensive analysis of the noise in the signal link is also conducted and the findings presented. A single-channel prototype is designed in 55 nm CMOS with a single 1.2 V supply voltage. The standalone ASIC testing highlights a time resolution of 4.20±0.04 ps for a minimum ionizing particle (MIP) which is equivalent to 32 pC charge. Additionally, a linear time-over-threshold (ToT) response from 1 to 12 MIP is attained and typical 15 mW power consumption realized.